1 /*
2 * SPDX-License-Identifier: Apache-2.0
3 *
4 * Copyright (C) 2022-2023, Intel Corporation
5 *
6 */
7
8 #include <zephyr/drivers/clock_control.h>
9 #include <zephyr/dt-bindings/clock/intel_socfpga_clock.h>
10 #include <zephyr/logging/log.h>
11
12 #include "clock_control_agilex5_ll.h"
13
14 #define DT_DRV_COMPAT intel_agilex5_clock
15
16 LOG_MODULE_REGISTER(clock_control_agilex5, CONFIG_CLOCK_CONTROL_LOG_LEVEL);
17
18 struct clock_control_config {
19 DEVICE_MMIO_ROM;
20 };
21
22 struct clock_control_data {
23 DEVICE_MMIO_RAM;
24 };
25
clock_init(const struct device * dev)26 static int clock_init(const struct device *dev)
27 {
28 DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE);
29
30 /* Initialize the low layer clock driver */
31 clock_agilex5_ll_init(DEVICE_MMIO_GET(dev));
32
33 LOG_INF("Intel Agilex5 clock driver initialized!");
34
35 return 0;
36 }
37
clock_get_rate(const struct device * dev,clock_control_subsys_t sub_system,uint32_t * rate)38 static int clock_get_rate(const struct device *dev, clock_control_subsys_t sub_system,
39 uint32_t *rate)
40 {
41 ARG_UNUSED(dev);
42
43 switch ((intptr_t)sub_system) {
44 case INTEL_SOCFPGA_CLOCK_MPU:
45 *rate = get_mpu_clk();
46 break;
47
48 case INTEL_SOCFPGA_CLOCK_WDT:
49 *rate = get_wdt_clk();
50 break;
51
52 case INTEL_SOCFPGA_CLOCK_UART:
53 *rate = get_uart_clk();
54 break;
55
56 case INTEL_SOCFPGA_CLOCK_MMC:
57 *rate = get_mmc_clk();
58 break;
59
60 case INTEL_SOCFPGA_CLOCK_TIMER:
61 *rate = get_timer_clk();
62 break;
63
64 default:
65 LOG_ERR("Clock ID %ld is not supported\n", (intptr_t)sub_system);
66 return -ENOTSUP;
67 }
68
69 return 0;
70 }
71
72 static const struct clock_control_driver_api clock_api = {.get_rate = clock_get_rate};
73
74 #define CLOCK_CONTROL_DEVICE(_inst) \
75 \
76 static struct clock_control_data clock_control_data_##_inst; \
77 \
78 static const struct clock_control_config clock_control_config_##_inst = { \
79 DEVICE_MMIO_ROM_INIT(DT_DRV_INST(_inst)), \
80 }; \
81 \
82 DEVICE_DT_INST_DEFINE(_inst, clock_init, NULL, &clock_control_data_##_inst, \
83 &clock_control_config_##_inst, PRE_KERNEL_1, \
84 CONFIG_CLOCK_CONTROL_INIT_PRIORITY, &clock_api);
85
86 DT_INST_FOREACH_STATUS_OKAY(CLOCK_CONTROL_DEVICE)
87
