1 /*
2 * Copyright (c) 2022 Intel Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6 #include <zephyr/device.h>
7 #include <zephyr/drivers/clock_control/clock_control_adsp.h>
8 #include <zephyr/drivers/clock_control.h>
9
cavs_clock_ctrl_set_rate(const struct device * clk,clock_control_subsys_t sys,clock_control_subsys_rate_t rate)10 static int cavs_clock_ctrl_set_rate(const struct device *clk,
11 clock_control_subsys_t sys,
12 clock_control_subsys_rate_t rate)
13 {
14 uint32_t freq_idx = (uint32_t)rate;
15
16 return adsp_clock_set_cpu_freq(freq_idx);
17 }
18
cavs_clock_ctrl_init(const struct device * dev)19 static int cavs_clock_ctrl_init(const struct device *dev)
20 {
21 /* Nothing to do. All initialisation should've been handled
22 * by SOC level driver.
23 */
24 return 0;
25 }
26
27 static const struct clock_control_driver_api cavs_clock_api = {
28 .set_rate = cavs_clock_ctrl_set_rate
29 };
30
31 DEVICE_DT_DEFINE(DT_NODELABEL(clkctl), &cavs_clock_ctrl_init, NULL,
32 NULL, NULL, POST_KERNEL,
33 CONFIG_CLOCK_CONTROL_INIT_PRIORITY, &cavs_clock_api);
34
