1 /*
2 * SPDX-License-Identifier: Apache-2.0
3 *
4 * Copyright (C) 2021-2022, Intel Corporation
5 *
6 */
7
8 #include <zephyr/drivers/clock_control.h>
9 #include <zephyr/drivers/clock_control/clock_agilex_ll.h>
10 #include <zephyr/dt-bindings/clock/intel_socfpga_clock.h>
11
clk_get_rate(const struct device * dev,clock_control_subsys_t sub_system,uint32_t * rate)12 static int clk_get_rate(const struct device *dev,
13 clock_control_subsys_t sub_system,
14 uint32_t *rate)
15 {
16 ARG_UNUSED(dev);
17
18 switch ((intptr_t) sub_system) {
19 case INTEL_SOCFPGA_CLOCK_MPU:
20 *rate = get_mpu_clk();
21 break;
22 case INTEL_SOCFPGA_CLOCK_WDT:
23 *rate = get_wdt_clk();
24 break;
25 case INTEL_SOCFPGA_CLOCK_UART:
26 *rate = get_uart_clk();
27 break;
28 case INTEL_SOCFPGA_CLOCK_MMC:
29 *rate = get_mmc_clk();
30 break;
31 default:
32 return -ENOTSUP;
33 }
34
35 return 0;
36 }
37
38 static const struct clock_control_driver_api clk_api = {
39 .get_rate = clk_get_rate
40 };
41
42 DEVICE_DT_DEFINE(DT_NODELABEL(clock), NULL, NULL, NULL, NULL,
43 PRE_KERNEL_1, CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
44 &clk_api);
45
