1 /*
2 * Copyright (c) 2001-2019, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #define CC_PAL_LOG_CUR_COMPONENT CC_LOG_MASK_CC_SYM_DRIVER
8
9 #include "cc_pal_mem.h"
10 #include "cc_pal_log.h"
11 #include "bypass_driver.h"
12 #include "driver_defs.h"
13 #include "cc_sym_error.h"
14 #include "cc_hal.h"
15 #include "cc_hal_plat.h"
16 #include "cc_regs.h"
17 #include "dx_crys_kernel.h"
18
19
20 /******************************************************************************
21 * PRIVATE FUNCTIONS
22 ******************************************************************************/
23
ProcessBypass(CCBuffInfo_t * pInputBuffInfo,dataAddrType_t inputDataAddrType,CCBuffInfo_t * pOutputBuffInfo,dataAddrType_t outputDataAddrType,uint32_t blockSize)24 drvError_t ProcessBypass(CCBuffInfo_t *pInputBuffInfo, dataAddrType_t inputDataAddrType,
25 CCBuffInfo_t *pOutputBuffInfo, dataAddrType_t outputDataAddrType,
26 uint32_t blockSize)
27 {
28 drvError_t drvRc = BYPASS_DRV_OK;
29 uint32_t irrVal = 0;
30 uint32_t regVal = 0;
31 uint32_t inputDataAddr, outputDataAddr;
32
33 /* check input parameters */
34 if ( (pInputBuffInfo == NULL) || (pOutputBuffInfo == NULL)) {
35 return BYPASS_DRV_INVALID_USER_DATA_BUFF_POINTER_ERROR;
36 }
37
38 /* verify min block size */
39 if (blockSize == 0)
40 return BYPASS_DRV_ILLEGAL_BLOCK_SIZE_ERROR;
41
42 /* verify aes valid input addr type */
43 if( (inputDataAddrType != SRAM_ADDR) &&
44 (inputDataAddrType != DLLI_ADDR) ) {
45 return BYPASS_DRV_ILLEGAL_INPUT_ADDR_MEM_ERROR;
46 }
47
48 /* verify aes valid output addr type for ecb, cbc, ctr */
49 if( (outputDataAddrType != SRAM_ADDR) &&
50 (outputDataAddrType != DLLI_ADDR) ) {
51 return BYPASS_DRV_ILLEGAL_OUTPUT_ADDR_MEM_ERROR;
52 }
53
54 /* make sure sym engines are ready to use */
55 CC_HAL_WAIT_ON_CRYPTO_BUSY();
56
57 /* clear all interrupts before starting the engine */
58 CC_HalClearInterruptBit(0xFFFFFFFFUL);
59
60 /* mask dma interrupts which are not required */
61 irrVal = CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_IMR));
62 CC_REG_FLD_SET(HOST_RGF, HOST_IMR, SRAM_TO_DIN_MASK, irrVal, 1);
63 CC_REG_FLD_SET(HOST_RGF, HOST_IMR, DOUT_TO_SRAM_MASK, irrVal, 1);
64 CC_REG_FLD_SET(HOST_RGF, HOST_IMR, MEM_TO_DIN_MASK, irrVal, 1);
65 CC_REG_FLD_SET(HOST_RGF, HOST_IMR, DOUT_TO_MEM_MASK, irrVal, 1);
66 CC_REG_FLD_SET(HOST_RGF, HOST_IMR, SYM_DMA_COMPLETED_MASK, irrVal, 0);
67 CC_HalMaskInterrupt(irrVal);
68
69 /* configure DIN-BYPASS-DOUT */
70 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, CRYPTO_CTL) ,CONFIG_DIN_BYPASS_DOUT_VAL);
71
72 /* enable clock */
73 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_CLK_ENABLE) ,SET_CLOCK_ENABLE);
74 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, DMA_CLK_ENABLE) ,SET_CLOCK_ENABLE);
75
76 inputDataAddr = pInputBuffInfo->dataBuffAddr;
77 outputDataAddr = pOutputBuffInfo->dataBuffAddr;
78
79 /* configure the HW with the correct data buffer attributes (secure/non-secure) */
80 CC_REG_FLD_SET(HOST_RGF, AHBM_HNONSEC, AHB_READ_HNONSEC, regVal, pInputBuffInfo->dataBuffNs);
81 CC_REG_FLD_SET(HOST_RGF, AHBM_HNONSEC, AHB_WRITE_HNONSEC, regVal, pOutputBuffInfo->dataBuffNs);
82 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AHBM_HNONSEC) ,regVal);
83
84 /* configure destination address and size; set dout bit in irr */
85 if (outputDataAddrType == DLLI_ADDR){
86 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, DST_LLI_WORD0) ,outputDataAddr);
87 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, DST_LLI_WORD1) ,blockSize);
88 } else {
89 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, SRAM_DEST_ADDR) ,outputDataAddr);
90 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, DOUT_SRAM_BYTES_LEN) ,blockSize);
91 }
92
93 /* configure source address and size */
94 if (inputDataAddrType == DLLI_ADDR){
95 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, SRC_LLI_WORD0) ,inputDataAddr);
96 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, SRC_LLI_WORD1) ,blockSize);
97 } else {
98 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, SRAM_SRC_ADDR) ,inputDataAddr);
99 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, DIN_SRAM_BYTES_LEN) ,blockSize);
100 }
101
102 /* set dma completion bit in irr */
103 irrVal = 0;
104 CC_REG_FLD_SET(HOST_RGF, HOST_IRR, SYM_DMA_COMPLETED, irrVal, 1);
105 drvRc = CC_HalWaitInterrupt(irrVal);
106
107 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_CLK_ENABLE) ,SET_CLOCK_DISABLE);
108 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, DMA_CLK_ENABLE) ,SET_CLOCK_DISABLE);
109
110 return drvRc;
111 }
112
113
114
