1 /*
2 * Copyright (c) 2001-2022, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6 #include "mbedtls/build_info.h"
7
8 #if defined(MBEDTLS_GCM_C)
9
10 #include "cc_hal_plat.h"
11 #include "cc_regs.h"
12 #include "dx_crys_kernel.h"
13 #include "cc_pal_mem.h"
14 #include "cc_hal.h"
15 #include "aesgcm_driver.h"
16 #include "cc_pal_abort.h"
17 #include "cc_pal_mutex.h"
18 #include "cc_util_pm.h"
19
20 extern CC_PalMutex CCSymCryptoMutex;
21
22 /******************************************************************************
23 * PRIVATE FUNCTIONS
24 ******************************************************************************/
25
loadAesGcmGhashSubkey(AesGcmContext_t * pAesGcmCtx)26 void loadAesGcmGhashSubkey(AesGcmContext_t *pAesGcmCtx)
27 {
28 /* Set H as the GHASH Key */
29 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, GHASH_SUBKEY_0_0), pAesGcmCtx->H[0]);
30 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, GHASH_SUBKEY_0_1), pAesGcmCtx->H[1]);
31 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, GHASH_SUBKEY_0_2), pAesGcmCtx->H[2]);
32 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, GHASH_SUBKEY_0_3), pAesGcmCtx->H[3]);
33
34 return;
35 }
loadAesGcmKey(AesGcmContext_t * pAesGcmCtx)36 void loadAesGcmKey(AesGcmContext_t *pAesGcmCtx)
37 {
38 /* load key0 [127:0]*/
39 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_KEY_0_0) ,pAesGcmCtx->keyBuf[0]);
40 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_KEY_0_1) ,pAesGcmCtx->keyBuf[1]);
41 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_KEY_0_2) ,pAesGcmCtx->keyBuf[2]);
42 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_KEY_0_3) ,pAesGcmCtx->keyBuf[3]);
43
44 if (pAesGcmCtx->keySizeId > KEY_SIZE_128_BIT) {
45 /* load key0 [191:128]*/
46 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_KEY_0_4) ,pAesGcmCtx->keyBuf[4]);
47 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_KEY_0_5) ,pAesGcmCtx->keyBuf[5]);
48 }
49
50 if (pAesGcmCtx->keySizeId > KEY_SIZE_192_BIT) {
51 /* load key0 [255:191]*/
52 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_KEY_0_6) ,pAesGcmCtx->keyBuf[6]);
53 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_KEY_0_7) ,pAesGcmCtx->keyBuf[7]);
54 }
55
56 return;
57 }
58
inc32AesGcmJ0(AesGcmContext_t * pAesGcmCtx)59 void inc32AesGcmJ0(AesGcmContext_t *pAesGcmCtx)
60 {
61 uint32_t tmpWord = SWAP_ENDIAN(pAesGcmCtx->J0[3]);
62 /* --- Inc32 LSW --- */
63 /* Check overlap and inc. by 1 */
64 if (BITMASK(CC_BITS_IN_32BIT_WORD) != tmpWord) {
65 tmpWord++;
66 }
67 else {
68 tmpWord = 0;
69 }
70
71 CC_PalMemCopy(pAesGcmCtx->aesCntrBuf, pAesGcmCtx->J0, CC_AESGCM_GHASH_DIGEST_SIZE_BYTES);
72 pAesGcmCtx->aesCntrBuf[3] = SWAP_ENDIAN(tmpWord);
73
74 return;
75 }
76
loadAesGcmCntr(AesGcmContext_t * pAesGcmCtx)77 void loadAesGcmCntr(AesGcmContext_t *pAesGcmCtx)
78 {
79 /* Write the initial counter value */
80 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_CTR_0_0), pAesGcmCtx->aesCntrBuf[0]);
81 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_CTR_0_1), pAesGcmCtx->aesCntrBuf[1]);
82 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_CTR_0_2), pAesGcmCtx->aesCntrBuf[2]);
83 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_CTR_0_3), pAesGcmCtx->aesCntrBuf[3]);
84
85 return;
86 }
87
storeAesGcmCntr(AesGcmContext_t * pAesGcmCtx)88 void storeAesGcmCntr(AesGcmContext_t *pAesGcmCtx)
89 {
90 /* Read the AES counter value */
91 pAesGcmCtx->aesCntrBuf[0] = CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_CTR_0_0));
92 pAesGcmCtx->aesCntrBuf[1] = CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_CTR_0_1));
93 pAesGcmCtx->aesCntrBuf[2] = CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_CTR_0_2));
94 pAesGcmCtx->aesCntrBuf[3] = CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_CTR_0_3));
95
96 return;
97 }
98
loadAesGcmGhashIV(AesGcmContext_t * pAesGcmCtx)99 void loadAesGcmGhashIV(AesGcmContext_t *pAesGcmCtx)
100 {
101 /* Write the initial counter value according to mode */
102 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, GHASH_IV_0_0), pAesGcmCtx->ghashResBuf[0]);
103 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, GHASH_IV_0_1), pAesGcmCtx->ghashResBuf[1]);
104 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, GHASH_IV_0_2), pAesGcmCtx->ghashResBuf[2]);
105 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, GHASH_IV_0_3), pAesGcmCtx->ghashResBuf[3]);
106
107 return;
108 }
109
storeAesGcmGhashIV(AesGcmContext_t * pAesGcmCtx,CCBool storeInJ0)110 void storeAesGcmGhashIV(AesGcmContext_t *pAesGcmCtx, CCBool storeInJ0)
111 {
112 /* Write the result in GHASH Result Buffer */
113 pAesGcmCtx->ghashResBuf[0] = CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, GHASH_IV_0_0));
114 pAesGcmCtx->ghashResBuf[1] = CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, GHASH_IV_0_1));
115 pAesGcmCtx->ghashResBuf[2] = CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, GHASH_IV_0_2));
116 pAesGcmCtx->ghashResBuf[3] = CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, GHASH_IV_0_3));
117
118 if(CC_TRUE == storeInJ0) {
119 /* Write the result in J0 */
120 CC_PalMemCopy(pAesGcmCtx->J0, pAesGcmCtx->ghashResBuf, CC_AESGCM_GHASH_DIGEST_SIZE_BYTES);
121 }
122
123 return;
124 }
125
initAesGcm(AesGcmContext_t * pAesGcmCtx)126 drvError_t initAesGcm(AesGcmContext_t* pAesGcmCtx)
127 {
128 uint32_t auxReg = 0;
129 uint32_t irrVal = 0;
130
131 /* Verify user context pointer */
132 if (NULL == pAesGcmCtx) {
133 return AES_DRV_INVALID_USER_CONTEXT_POINTER_ERROR;
134 }
135
136 /* verify valid dir */
137 if ( (pAesGcmCtx->dir != CRYPTO_DIRECTION_ENCRYPT) &&
138 (pAesGcmCtx->dir != CRYPTO_DIRECTION_DECRYPT) ) {
139 return AES_DRV_ILLEGAL_OPERATION_DIRECTION_ERROR;
140 }
141
142 /* Set to 0x00 */
143 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_REMAINING_BYTES), 0x00);
144
145 /* Configure cores according to the process mode */
146 switch (pAesGcmCtx->processMode) {
147 case DRV_AESGCM_Process_CalcH:
148 /* Set cryptographic flow to AES */
149 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, CRYPTO_CTL), CONFIG_DIN_AES_DOUT_VAL);
150 /********************************************************************************/
151 /*** AES Configurations ***/
152 /********************************************************************************/
153 /* Set Direction: Enc */
154 CC_REG_FLD_SET(HOST_RGF, AES_CONTROL, DEC_KEY0, auxReg, CRYPTO_DIRECTION_ENCRYPT);
155 /* Set AES Mode to ECB */
156 CC_REG_FLD_SET(HOST_RGF, AES_CONTROL, MODE_KEY0, auxReg, CIPHER_ECB);
157 /* Set AES Key length */
158 CC_REG_FLD_SET(HOST_RGF, AES_CONTROL, NK_KEY0, auxReg, pAesGcmCtx->keySizeId);
159
160 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_CONTROL), auxReg);
161
162 /* Load Key */
163 loadAesGcmKey(pAesGcmCtx);
164
165 /* Set to 0x10 */
166 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_REMAINING_BYTES), AES_BLOCK_SIZE);
167
168 break;
169 case DRV_AESGCM_Process_CalcJ0_FirstPhase:
170 case DRV_AESGCM_Process_A:
171 /* Set the GHASH Engine to be ready to a new GHASH operation */
172 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, GHASH_INIT), GHASH_INIT_SET_VAL);
173 /* Falls through. */
174 case DRV_AESGCM_Process_CalcJ0_SecondPhase:
175 /* Set cryptographic flow to HASH */
176 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, CRYPTO_CTL), CONFIG_HASH_MODE_VAL);
177 /********************************************************************************/
178 /*** GHASH Configurations ***/
179 /********************************************************************************/
180 /* Set H as the GHASH Key */
181 loadAesGcmGhashSubkey(pAesGcmCtx);
182
183 /* Set '0' as the GHASH IV */
184 loadAesGcmGhashIV(pAesGcmCtx);
185
186 /* Set Hash select module */
187 CC_REG_FLD_SET(HOST_RGF, HASH_SEL_AES_MAC, HASH_SEL_AES_MAC, auxReg, HASH_SEL_HASH_MOD);
188 /* Set Ghash select module */
189 CC_REG_FLD_SET(HOST_RGF, HASH_SEL_AES_MAC, GHASH_SEL, auxReg, GHASH_SEL_GHASH_MOD);
190
191 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HASH_SEL_AES_MAC), auxReg);
192
193 /* Set '0' as the GHASH IV */
194 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HASH_XOR_DIN), HASH_XOR_DATA_VAL);
195
196 break;
197 case DRV_AESGCM_Process_DataIn:
198 /* Set cryptographic flow according to crypto direction */
199 if (CRYPTO_DIRECTION_ENCRYPT == pAesGcmCtx->dir) {
200 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, CRYPTO_CTL), CONFIG_AES_TO_HASH_AND_DOUT_VAL);
201 } else {
202 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, CRYPTO_CTL), CONFIG_DIN_AES_AND_HASH_VAL);
203 }
204 /********************************************************************************/
205 /*** AES Configurations ***/
206 /********************************************************************************/
207 /* Set Direction: Enc */
208 CC_REG_FLD_SET(HOST_RGF, AES_CONTROL, DEC_KEY0, auxReg, CRYPTO_DIRECTION_ENCRYPT);
209 /* Set AES Mode to CTR */
210 CC_REG_FLD_SET(HOST_RGF, AES_CONTROL, MODE_KEY0, auxReg, CIPHER_CTR);
211 /* Set AES Key length */
212 CC_REG_FLD_SET(HOST_RGF, AES_CONTROL, NK_KEY0, auxReg, pAesGcmCtx->keySizeId);
213
214 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_CONTROL), auxReg);
215
216 if(CC_FALSE == pAesGcmCtx->J0Inc32DoneFlg) {
217 inc32AesGcmJ0(pAesGcmCtx);
218 pAesGcmCtx->J0Inc32DoneFlg = CC_TRUE;
219 }
220
221 /* Load Counter */
222 loadAesGcmCntr(pAesGcmCtx);
223
224 /* Load Key */
225 loadAesGcmKey(pAesGcmCtx);
226
227 /* Set to data size */
228 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_REMAINING_BYTES), pAesGcmCtx->dataSize);
229
230 /********************************************************************************/
231 /*** GHASH Configurations ***/
232 /********************************************************************************/
233 /* Set H as the GHASH Key */
234 loadAesGcmGhashSubkey(pAesGcmCtx);
235 /* Set former GHASH result as the new GHASH_IV value */
236 loadAesGcmGhashIV(pAesGcmCtx);
237
238 /* Set Hash select module */
239 CC_REG_FLD_SET(HOST_RGF, HASH_SEL_AES_MAC, HASH_SEL_AES_MAC, auxReg, HASH_SEL_HASH_MOD);
240 /* Set Ghash select module */
241 CC_REG_FLD_SET(HOST_RGF, HASH_SEL_AES_MAC, GHASH_SEL, auxReg, GHASH_SEL_GHASH_MOD);
242
243 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HASH_SEL_AES_MAC), auxReg);
244
245 /* Set '0' as the GHASH IV */
246 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HASH_XOR_DIN), HASH_XOR_DATA_VAL);
247 break;
248 case DRV_AESGCM_Process_LenA_LenC:
249 /* Set cryptographic flow to HASH */
250 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, CRYPTO_CTL), CONFIG_HASH_MODE_VAL);
251 /********************************************************************************/
252 /*** GHASH Configurations ***/
253 /********************************************************************************/
254 /* Set H as the GHASH Key */
255 loadAesGcmGhashSubkey(pAesGcmCtx);
256 /* Set former GHASH result as the new GHASH_IV value */
257 loadAesGcmGhashIV(pAesGcmCtx);
258
259 /* Set Hash select module */
260 CC_REG_FLD_SET(HOST_RGF, HASH_SEL_AES_MAC, HASH_SEL_AES_MAC, auxReg, HASH_SEL_HASH_MOD);
261 /* Set Ghash select module */
262 CC_REG_FLD_SET(HOST_RGF, HASH_SEL_AES_MAC, GHASH_SEL, auxReg, GHASH_SEL_GHASH_MOD);
263
264 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HASH_SEL_AES_MAC), auxReg);
265
266 /* Set '0' as the GHASH IV */
267 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HASH_XOR_DIN), HASH_XOR_DATA_VAL);
268 break;
269 case DRV_AESGCM_Process_GctrFinal:
270 /* Set cryptographic flow to AES */
271 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, CRYPTO_CTL), CONFIG_DIN_AES_DOUT_VAL);
272 /********************************************************************************/
273 /*** AES Configurations ***/
274 /********************************************************************************/
275 /* Set Direction: Enc */
276 CC_REG_FLD_SET(HOST_RGF, AES_CONTROL, DEC_KEY0, auxReg, CRYPTO_DIRECTION_ENCRYPT);
277 /* Set AES Mode to CTR */
278 CC_REG_FLD_SET(HOST_RGF, AES_CONTROL, MODE_KEY0, auxReg, CIPHER_CTR);
279 /* Set AES Key length */
280 CC_REG_FLD_SET(HOST_RGF, AES_CONTROL, NK_KEY0, auxReg, pAesGcmCtx->keySizeId);
281
282 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_CONTROL), auxReg);
283
284 /* Load Counter */
285 CC_PalMemCopy(pAesGcmCtx->aesCntrBuf, pAesGcmCtx->J0, CC_AESGCM_GHASH_DIGEST_SIZE_BYTES);
286 loadAesGcmCntr(pAesGcmCtx);
287
288 /* Load Key */
289 loadAesGcmKey(pAesGcmCtx);
290
291 /* Copy GHASH result to the Input address */
292 CC_PalMemCopy(pAesGcmCtx->tempBuf, pAesGcmCtx->ghashResBuf, CC_AESGCM_GHASH_DIGEST_SIZE_BYTES);
293
294 /* Set to GHASH Output size */
295 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_REMAINING_BYTES), CC_AESGCM_GHASH_DIGEST_SIZE_BYTES);
296 break;
297 default:
298 return AES_DRV_ILLEGAL_OPERATION_MODE_ERROR;
299 }
300
301 /* make sure sym engines are ready to use */
302 CC_HAL_WAIT_ON_CRYPTO_BUSY();
303
304 /* clear all interrupts before starting the engine */
305 CC_HalClearInterruptBit(0xFFFFFFFFUL);
306
307 /* mask dma interrupts which are not required */
308 irrVal = CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_IMR));
309 CC_REG_FLD_SET(HOST_RGF, HOST_IMR, SRAM_TO_DIN_MASK, irrVal, 1);
310 CC_REG_FLD_SET(HOST_RGF, HOST_IMR, DOUT_TO_SRAM_MASK, irrVal, 1);
311 CC_REG_FLD_SET(HOST_RGF, HOST_IMR, MEM_TO_DIN_MASK, irrVal, 1);
312 CC_REG_FLD_SET(HOST_RGF, HOST_IMR, DOUT_TO_MEM_MASK, irrVal, 1);
313 CC_REG_FLD_SET(HOST_RGF, HOST_IMR, SYM_DMA_COMPLETED_MASK, irrVal, 0);
314 CC_HalMaskInterrupt(irrVal);
315
316 return AES_DRV_OK;
317 }
318
319
320 /******************************************************************************
321 * PUBLIC FUNCTIONS
322 ******************************************************************************/
323
ProcessAesGcm(AesGcmContext_t * pAesGcmCtx,CCBuffInfo_t * pInputBuffInfo,CCBuffInfo_t * pOutputBuffInfo,uint32_t blockSize)324 drvError_t ProcessAesGcm(AesGcmContext_t *pAesGcmCtx, CCBuffInfo_t *pInputBuffInfo, CCBuffInfo_t *pOutputBuffInfo, uint32_t blockSize)
325 {
326 drvError_t drvRc = AES_DRV_OK;
327 uint32_t irrVal = 0;
328 uint32_t regVal = 0;
329 uint32_t inputDataAddr, outputDataAddr;
330
331 /* check input parameters */
332 if ( (pInputBuffInfo == NULL) || (pOutputBuffInfo == NULL)) {
333 return AES_DRV_INVALID_USER_DATA_BUFF_POINTER_ERROR;
334 }
335
336 /* Verify user context pointer */
337 if (NULL == pAesGcmCtx) {
338 return AES_DRV_INVALID_USER_CONTEXT_POINTER_ERROR;
339 }
340
341 /* Verify valid block size */
342 if (blockSize >= DLLI_MAX_BUFF_SIZE) {
343 return AES_DRV_ILLEGAL_MEM_SIZE_ERROR;
344 }
345
346 /* Lock mutex for all hw operation */
347 if (CC_PalMutexLock(&CCSymCryptoMutex, CC_INFINITE) != 0) {
348 CC_PalAbort("Fail to acquire mutex\n");
349 }
350
351 /* increase CC counter at the beginning of each operation */
352 drvRc = CC_IS_WAKE;
353 if (drvRc != 0) {
354 CC_PalAbort("Fail to increase PM counter\n");
355 }
356
357 /********************************************************************************/
358 /*** Enable Clocks ***/
359 /********************************************************************************/
360 /* Enable AES clock */
361 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_CLK_ENABLE), SET_CLOCK_ENABLE);
362 /* Enable Hash clock */
363 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HASH_CLK_ENABLE), SET_CLOCK_ENABLE);
364 /* Enable DMA clock */
365 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, DMA_CLK_ENABLE), SET_CLOCK_ENABLE);
366
367 /* Registers initializations */
368 drvRc = initAesGcm(pAesGcmCtx);
369 if (drvRc != AES_DRV_OK) {
370 goto ProcessExit;
371 }
372
373 inputDataAddr = pInputBuffInfo->dataBuffAddr;
374 outputDataAddr = pOutputBuffInfo->dataBuffAddr;
375
376 /* configure the HW with the correct data buffer attributes (secure/non-secure) */
377 CC_REG_FLD_SET(HOST_RGF, AHBM_HNONSEC, AHB_READ_HNONSEC, regVal, pInputBuffInfo->dataBuffNs);
378 CC_REG_FLD_SET(HOST_RGF, AHBM_HNONSEC, AHB_WRITE_HNONSEC, regVal, pOutputBuffInfo->dataBuffNs);
379 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AHBM_HNONSEC) ,regVal);
380
381 /* For AES operations only */
382 if((DRV_AESGCM_Process_CalcH == pAesGcmCtx->processMode) ||
383 (DRV_AESGCM_Process_DataIn == pAesGcmCtx->processMode) ||
384 (DRV_AESGCM_Process_GctrFinal == pAesGcmCtx->processMode)) {
385 /* Configure destination address and size */
386 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, DST_LLI_WORD0) ,outputDataAddr);
387 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, DST_LLI_WORD1) ,blockSize);
388 }
389
390 /* Configure source address and size */
391 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, SRC_LLI_WORD0) ,inputDataAddr);
392 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, SRC_LLI_WORD1) ,blockSize); // Kick operation
393
394 /* Set DMA completion bit in IRR */
395 CC_REG_FLD_SET(HOST_RGF, HOST_IRR, SYM_DMA_COMPLETED, irrVal, 1);
396
397 /* Wait for completion */
398 drvRc = CC_HalWaitInterrupt(irrVal);
399 if (drvRc != AES_DRV_OK) {
400 goto ProcessExit_Err;
401 }
402 /* Post-processing */
403 switch (pAesGcmCtx->processMode) {
404 case DRV_AESGCM_Process_CalcH:
405 break;
406 case DRV_AESGCM_Process_CalcJ0_FirstPhase:
407 storeAesGcmGhashIV(pAesGcmCtx, CC_FALSE);
408 break;
409 case DRV_AESGCM_Process_CalcJ0_SecondPhase:
410 storeAesGcmGhashIV(pAesGcmCtx, CC_TRUE);
411 break;
412 case DRV_AESGCM_Process_A:
413 storeAesGcmGhashIV(pAesGcmCtx, CC_FALSE);
414 break;
415 case DRV_AESGCM_Process_DataIn:
416 storeAesGcmCntr(pAesGcmCtx);
417 storeAesGcmGhashIV(pAesGcmCtx, CC_FALSE);
418 break;
419 case DRV_AESGCM_Process_LenA_LenC:
420 storeAesGcmGhashIV(pAesGcmCtx, CC_FALSE);
421 break;
422 case DRV_AESGCM_Process_GctrFinal:
423 break;
424 default:
425 drvRc = AES_DRV_ILLEGAL_OPERATION_MODE_ERROR;
426 break;
427 }
428
429 ProcessExit:
430
431 /********************************************************************************/
432 /*** Reset to default values in case of operation completion ***/
433 /********************************************************************************/
434 if((DRV_AESGCM_Process_CalcH != pAesGcmCtx->processMode) &&
435 (DRV_AESGCM_Process_GctrFinal != pAesGcmCtx->processMode)) {
436 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HASH_PAD_EN) ,1);
437 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AUTO_HW_PADDING) ,0);
438 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HASH_PAD_CFG) ,0);
439 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HASH_SEL_AES_MAC), 0);
440 }
441
442 ProcessExit_Err:
443 /********************************************************************************/
444 /*** Disable Clocks ***/
445 /********************************************************************************/
446 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, DMA_CLK_ENABLE), SET_CLOCK_DISABLE);
447 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HASH_CLK_ENABLE), SET_CLOCK_DISABLE);
448 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_CLK_ENABLE), SET_CLOCK_DISABLE);
449
450 /* decrease CC counter at the end of each operation */
451 if (CC_IS_IDLE != 0) {
452 CC_PalAbort("Fail to decrease PM counter\n");
453 }
454
455 /* Release mutex */
456 if (CC_PalMutexUnlock(&CCSymCryptoMutex) != 0) {
457 CC_PalAbort("Fail to release mutex\n");
458 }
459
460 return drvRc;
461 }
462 #endif
463
