1 /*
2 * Copyright (c) 2019, Texas Instruments Incorporated
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT ti_cc13xx_cc26xx_rtc_timer
8
9 /*
10 * TI SimpleLink CC13X2/CC26X2 RTC-based system timer
11 *
12 * This system timer implementation supports both tickless and ticking modes.
13 * RTC counts continually in 64-bit mode and timeouts are
14 * scheduled using the RTC comparator. An interrupt is triggered whenever
15 * the comparator value set is reached.
16 */
17
18 #include <zephyr/init.h>
19 #include <soc.h>
20 #include <zephyr/drivers/clock_control.h>
21 #include <zephyr/drivers/timer/system_timer.h>
22 #include <zephyr/irq.h>
23 #include <zephyr/spinlock.h>
24 #include <zephyr/sys_clock.h>
25 #include <zephyr/sys/util.h>
26
27 #include <driverlib/interrupt.h>
28 #include <driverlib/aon_rtc.h>
29 #include <driverlib/aon_event.h>
30
31 #define RTC_COUNTS_PER_SEC 0x100000000ULL
32
33 /* Number of counts per rtc timer cycle */
34 #define RTC_COUNTS_PER_CYCLE (RTC_COUNTS_PER_SEC / \
35 sys_clock_hw_cycles_per_sec())
36
37 /* Number of counts per system clock tick */
38 #define RTC_COUNTS_PER_TICK (RTC_COUNTS_PER_SEC / \
39 CONFIG_SYS_CLOCK_TICKS_PER_SEC)
40
41 /* Number of RTC cycles per system clock tick */
42 #define CYCLES_PER_TICK (sys_clock_hw_cycles_per_sec() / \
43 CONFIG_SYS_CLOCK_TICKS_PER_SEC)
44
45 /*
46 * Maximum number of ticks.
47 */
48 #define MAX_CYC 0x7FFFFFFFFFFFULL
49 #define MAX_TICKS (MAX_CYC / RTC_COUNTS_PER_TICK)
50
51 /*
52 * Due to the nature of clock synchronization, the comparator cannot be set
53 * to a value that is too close to the current time. This constant defines
54 * a safe threshold for the comparator.
55 */
56 #define COMPARE_MARGIN 6
57
58 /* RTC count of the last announce call, rounded down to tick boundary. */
59 static volatile uint64_t rtc_last;
60
61 #ifdef CONFIG_TICKLESS_KERNEL
62 static struct k_spinlock lock;
63 #else
64 static uint64_t nextThreshold = RTC_COUNTS_PER_TICK;
65 #endif /* CONFIG_TICKLESS_KERNEL */
66
67
setThreshold(uint32_t next)68 static void setThreshold(uint32_t next)
69 {
70 uint32_t now;
71 unsigned int key;
72
73 key = irq_lock();
74
75 /* get the current RTC count corresponding to compare window */
76 now = AONRTCCurrentCompareValueGet();
77
78 /* if next is too soon, set at least one RTC tick in future */
79 /* assume next never be more than half the maximum 32 bit count value */
80 if ((next - now) > (uint32_t)0x80000000) {
81 /* now is past next */
82 next = now + COMPARE_MARGIN;
83 } else if ((now + COMPARE_MARGIN - next) < (uint32_t)0x80000000) {
84 if (next < now + COMPARE_MARGIN) {
85 next = now + COMPARE_MARGIN;
86 }
87 }
88
89 /* set next compare threshold in RTC */
90 AONRTCCompareValueSet(AON_RTC_CH0, next);
91
92 irq_unlock(key);
93 }
94
rtc_isr(const void * arg)95 void rtc_isr(const void *arg)
96 {
97 #ifndef CONFIG_TICKLESS_KERNEL
98 uint64_t newThreshold;
99 uint32_t next;
100 #else
101 uint64_t ticks, currCount;
102 #endif
103
104 ARG_UNUSED(arg);
105
106 AONRTCEventClear(AON_RTC_CH0);
107
108 #ifdef CONFIG_TICKLESS_KERNEL
109 k_spinlock_key_t key = k_spin_lock(&lock);
110 currCount = (uint64_t)AONRTCCurrent64BitValueGet();
111 ticks = (currCount - rtc_last) / RTC_COUNTS_PER_TICK;
112
113 rtc_last += ticks * RTC_COUNTS_PER_TICK;
114 k_spin_unlock(&lock, key);
115
116 sys_clock_announce(ticks);
117
118 #else /* !CONFIG_TICKLESS_KERNEL */
119
120 /* calculate new 64-bit RTC count for next interrupt */
121 newThreshold = nextThreshold + RTC_COUNTS_PER_TICK;
122
123 next = (uint32_t)((uint64_t)newThreshold >> 16);
124 setThreshold(next);
125
126 nextThreshold = newThreshold;
127
128 rtc_last += RTC_COUNTS_PER_TICK;
129
130 sys_clock_announce(1);
131
132 #endif /* CONFIG_TICKLESS_KERNEL */
133 }
134
initDevice(void)135 static void initDevice(void)
136 {
137 AONRTCDisable();
138 AONRTCReset();
139
140 HWREG(AON_RTC_BASE + AON_RTC_O_SYNC) = 1;
141 /* read sync register to complete reset */
142 HWREG(AON_RTC_BASE + AON_RTC_O_SYNC);
143
144 AONRTCEventClear(AON_RTC_CH0);
145 IntPendClear(INT_AON_RTC_COMB);
146
147 HWREG(AON_RTC_BASE + AON_RTC_O_SYNC);
148 }
149
startDevice(void)150 static void startDevice(void)
151 {
152 uint32_t compare;
153 uint64_t period;
154 unsigned int key;
155
156 key = irq_lock();
157
158 /* reset timer */
159 AONRTCReset();
160 AONRTCEventClear(AON_RTC_CH0);
161 IntPendClear(INT_AON_RTC_COMB);
162
163 /*
164 * set the compare register to one period.
165 * For a very small period round up to interrupt upon 4th tick in
166 * compare register
167 */
168 period = RTC_COUNTS_PER_TICK;
169 if (period < 0x40000) {
170 compare = 0x4; /* 4 * 15.5us ~= 62us */
171 } else {
172 /* else, interrupt on first period expiration */
173 compare = period >> 16;
174 }
175
176 /* set the compare value at the RTC */
177 AONRTCCompareValueSet(AON_RTC_CH0, compare);
178
179 /* enable compare channel 0 */
180 AONEventMcuWakeUpSet(AON_EVENT_MCU_WU0, AON_EVENT_RTC0);
181 AONRTCChannelEnable(AON_RTC_CH0);
182 AONRTCCombinedEventConfig(AON_RTC_CH0);
183
184 /* start timer */
185 AONRTCEnable();
186
187 irq_unlock(key);
188 }
189
sys_clock_set_timeout(int32_t ticks,bool idle)190 void sys_clock_set_timeout(int32_t ticks, bool idle)
191 {
192 ARG_UNUSED(idle);
193
194 #ifdef CONFIG_TICKLESS_KERNEL
195
196 ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks;
197 ticks = CLAMP(ticks - 1, 0, (int32_t) MAX_TICKS);
198
199 k_spinlock_key_t key = k_spin_lock(&lock);
200
201 /* Compute number of RTC cycles until the next timeout. */
202 uint64_t count = AONRTCCurrent64BitValueGet();
203 uint64_t timeout = ticks * RTC_COUNTS_PER_TICK +
204 (count - rtc_last);
205
206 /* Round to the nearest tick boundary. */
207 timeout = DIV_ROUND_UP(timeout, RTC_COUNTS_PER_TICK) *
208 RTC_COUNTS_PER_TICK;
209 timeout = MIN(timeout, MAX_CYC);
210 timeout += rtc_last;
211
212 /* Set the comparator */
213 setThreshold(timeout >> 16);
214
215 k_spin_unlock(&lock, key);
216 #endif /* CONFIG_TICKLESS_KERNEL */
217 }
218
sys_clock_elapsed(void)219 uint32_t sys_clock_elapsed(void)
220 {
221 uint32_t ret = (AONRTCCurrent64BitValueGet() - rtc_last) /
222 RTC_COUNTS_PER_TICK;
223
224 return ret;
225 }
226
sys_clock_cycle_get_32(void)227 uint32_t sys_clock_cycle_get_32(void)
228 {
229 return (uint32_t)(AONRTCCurrent64BitValueGet() / RTC_COUNTS_PER_CYCLE);
230 }
231
sys_clock_cycle_get_64(void)232 uint64_t sys_clock_cycle_get_64(void)
233 {
234 return AONRTCCurrent64BitValueGet() / RTC_COUNTS_PER_CYCLE;
235 }
236
sys_clock_driver_init(void)237 static int sys_clock_driver_init(void)
238 {
239
240 rtc_last = 0U;
241
242 initDevice();
243 startDevice();
244
245 /* Enable RTC interrupt. */
246 IRQ_CONNECT(DT_INST_IRQN(0),
247 DT_INST_IRQ(0, priority),
248 rtc_isr, 0, 0);
249 irq_enable(DT_INST_IRQN(0));
250
251 return 0;
252 }
253
254 SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2,
255 CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
256
