1 /*
2 * Copyright (c) 2022 Vestas Wind Systems A/S
3 * Copyright (c) 2022 Blue Clover
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #include <zephyr/drivers/can.h>
9 #include <zephyr/drivers/can/can_mcan.h>
10 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
11 #include <zephyr/drivers/clock_control.h>
12 #include <zephyr/drivers/pinctrl.h>
13 #include <zephyr/kernel.h>
14 #include <stm32_ll_rcc.h>
15 #include <zephyr/logging/log.h>
16 #include <zephyr/irq.h>
17
18 LOG_MODULE_REGISTER(can_stm32h7, CONFIG_CAN_LOG_LEVEL);
19
20 #define DT_DRV_COMPAT st_stm32h7_fdcan
21
22 struct can_stm32h7_config {
23 mm_reg_t base;
24 mem_addr_t mrba;
25 mem_addr_t mram;
26 void (*config_irq)(void);
27 const struct pinctrl_dev_config *pcfg;
28 struct stm32_pclken pclken;
29 };
30
can_stm32h7_read_reg(const struct device * dev,uint16_t reg,uint32_t * val)31 static int can_stm32h7_read_reg(const struct device *dev, uint16_t reg, uint32_t *val)
32 {
33 const struct can_mcan_config *mcan_cfg = dev->config;
34 const struct can_stm32h7_config *stm32h7_cfg = mcan_cfg->custom;
35
36 return can_mcan_sys_read_reg(stm32h7_cfg->base, reg, val);
37 }
38
can_stm32h7_write_reg(const struct device * dev,uint16_t reg,uint32_t val)39 static int can_stm32h7_write_reg(const struct device *dev, uint16_t reg, uint32_t val)
40 {
41 const struct can_mcan_config *mcan_cfg = dev->config;
42 const struct can_stm32h7_config *stm32h7_cfg = mcan_cfg->custom;
43
44 return can_mcan_sys_write_reg(stm32h7_cfg->base, reg, val);
45 }
46
can_stm32h7_read_mram(const struct device * dev,uint16_t offset,void * dst,size_t len)47 static int can_stm32h7_read_mram(const struct device *dev, uint16_t offset, void *dst, size_t len)
48 {
49 const struct can_mcan_config *mcan_cfg = dev->config;
50 const struct can_stm32h7_config *stm32h7_cfg = mcan_cfg->custom;
51
52 return can_mcan_sys_read_mram(stm32h7_cfg->mram, offset, dst, len);
53 }
54
can_stm32h7_write_mram(const struct device * dev,uint16_t offset,const void * src,size_t len)55 static int can_stm32h7_write_mram(const struct device *dev, uint16_t offset, const void *src,
56 size_t len)
57 {
58 const struct can_mcan_config *mcan_cfg = dev->config;
59 const struct can_stm32h7_config *stm32h7_cfg = mcan_cfg->custom;
60
61 return can_mcan_sys_write_mram(stm32h7_cfg->mram, offset, src, len);
62 }
63
can_stm32h7_clear_mram(const struct device * dev,uint16_t offset,size_t len)64 static int can_stm32h7_clear_mram(const struct device *dev, uint16_t offset, size_t len)
65 {
66 const struct can_mcan_config *mcan_cfg = dev->config;
67 const struct can_stm32h7_config *stm32h7_cfg = mcan_cfg->custom;
68
69 return can_mcan_sys_clear_mram(stm32h7_cfg->mram, offset, len);
70 }
71
can_stm32h7_get_core_clock(const struct device * dev,uint32_t * rate)72 static int can_stm32h7_get_core_clock(const struct device *dev, uint32_t *rate)
73 {
74 const uint32_t rate_tmp = LL_RCC_GetFDCANClockFreq(LL_RCC_FDCAN_CLKSOURCE);
75
76 ARG_UNUSED(dev);
77
78 if (rate_tmp == LL_RCC_PERIPH_FREQUENCY_NO) {
79 LOG_ERR("Can't read core clock");
80 return -EIO;
81 }
82
83 *rate = rate_tmp;
84
85 LOG_DBG("rate=%d", *rate);
86
87 return 0;
88 }
89
can_stm32h7_clock_enable(const struct device * dev)90 static int can_stm32h7_clock_enable(const struct device *dev)
91 {
92 const struct can_mcan_config *mcan_cfg = dev->config;
93 const struct can_stm32h7_config *stm32h7_cfg = mcan_cfg->custom;
94 const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
95 int ret;
96
97 LL_RCC_SetFDCANClockSource(LL_RCC_FDCAN_CLKSOURCE_PLL1Q);
98
99 if (!device_is_ready(clk)) {
100 LOG_ERR("clock control device not ready");
101 return -ENODEV;
102 }
103
104 ret = clock_control_on(clk, (clock_control_subsys_t)&stm32h7_cfg->pclken);
105 if (ret != 0) {
106 LOG_ERR("failure enabling clock");
107 return ret;
108 }
109
110 if (!LL_RCC_PLL1Q_IsEnabled()) {
111 LOG_ERR("PLL1Q clock must be enabled!");
112 return -EIO;
113 }
114
115 return 0;
116 }
117
can_stm32h7_init(const struct device * dev)118 static int can_stm32h7_init(const struct device *dev)
119 {
120 const struct can_mcan_config *mcan_cfg = dev->config;
121 const struct can_stm32h7_config *stm32h7_cfg = mcan_cfg->custom;
122 int ret;
123
124 /* Configure dt provided device signals when available */
125 ret = pinctrl_apply_state(stm32h7_cfg->pcfg, PINCTRL_STATE_DEFAULT);
126 if (ret != 0) {
127 LOG_ERR("CAN pinctrl setup failed (%d)", ret);
128 return ret;
129 }
130
131 ret = can_stm32h7_clock_enable(dev);
132 if (ret != 0) {
133 return ret;
134 }
135
136 ret = can_mcan_configure_mram(dev, stm32h7_cfg->mrba, stm32h7_cfg->mram);
137 if (ret != 0) {
138 return ret;
139 }
140
141 ret = can_mcan_init(dev);
142 if (ret != 0) {
143 return ret;
144 }
145
146 stm32h7_cfg->config_irq();
147
148 return 0;
149 }
150
151 static const struct can_driver_api can_stm32h7_driver_api = {
152 .get_capabilities = can_mcan_get_capabilities,
153 .start = can_mcan_start,
154 .stop = can_mcan_stop,
155 .set_mode = can_mcan_set_mode,
156 .set_timing = can_mcan_set_timing,
157 .send = can_mcan_send,
158 .add_rx_filter = can_mcan_add_rx_filter,
159 .remove_rx_filter = can_mcan_remove_rx_filter,
160 .get_state = can_mcan_get_state,
161 #ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY
162 .recover = can_mcan_recover,
163 #endif
164 .get_core_clock = can_stm32h7_get_core_clock,
165 .get_max_bitrate = can_mcan_get_max_bitrate,
166 .get_max_filters = can_mcan_get_max_filters,
167 .set_state_change_callback = can_mcan_set_state_change_callback,
168 /* Timing limits are per the STM32H7 Reference Manual (RM0433 Rev 7),
169 * section 56.5.7, FDCAN nominal bit timing and prescaler register
170 * (FDCAN_NBTP).
171 *
172 * Beware that the reference manual contains a bug regarding the minimum
173 * values for nominal phase segments. Valid register values are 1 and up.
174 */
175 .timing_min = CAN_MCAN_TIMING_MIN_INITIALIZER,
176 .timing_max = CAN_MCAN_TIMING_MAX_INITIALIZER,
177 #ifdef CONFIG_CAN_FD_MODE
178 .set_timing_data = can_mcan_set_timing_data,
179 /* Data timing limits are per the STM32H7 Reference Manual
180 * (RM0433 Rev 7), section 56.5.3, FDCAN data bit timing and prescaler
181 * register (FDCAN_DBTP).
182 */
183 .timing_data_min = CAN_MCAN_TIMING_DATA_MIN_INITIALIZER,
184 .timing_data_max = CAN_MCAN_TIMING_DATA_MAX_INITIALIZER,
185 #endif
186 };
187
188 static const struct can_mcan_ops can_stm32h7_ops = {
189 .read_reg = can_stm32h7_read_reg,
190 .write_reg = can_stm32h7_write_reg,
191 .read_mram = can_stm32h7_read_mram,
192 .write_mram = can_stm32h7_write_mram,
193 .clear_mram = can_stm32h7_clear_mram,
194 };
195
196 #define CAN_STM32H7_MCAN_INIT(n) \
197 CAN_MCAN_DT_INST_BUILD_ASSERT_MRAM_CFG(n); \
198 BUILD_ASSERT(CAN_MCAN_DT_INST_MRAM_ELEMENTS_SIZE(n) <= \
199 CAN_MCAN_DT_INST_MRAM_SIZE(n), \
200 "Insufficient Message RAM size to hold elements"); \
201 \
202 static void stm32h7_mcan_irq_config_##n(void); \
203 \
204 PINCTRL_DT_INST_DEFINE(n); \
205 CAN_MCAN_DT_INST_CALLBACKS_DEFINE(n, can_stm32h7_cbs_##n); \
206 \
207 static const struct can_stm32h7_config can_stm32h7_cfg_##n = { \
208 .base = CAN_MCAN_DT_INST_MCAN_ADDR(n), \
209 .mrba = CAN_MCAN_DT_INST_MRBA(n), \
210 .mram = CAN_MCAN_DT_INST_MRAM_ADDR(n), \
211 .config_irq = stm32h7_mcan_irq_config_##n, \
212 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
213 .pclken = { \
214 .enr = DT_INST_CLOCKS_CELL(n, bits), \
215 .bus = DT_INST_CLOCKS_CELL(n, bus), \
216 }, \
217 }; \
218 \
219 static const struct can_mcan_config can_mcan_cfg_##n = \
220 CAN_MCAN_DT_CONFIG_INST_GET(n, &can_stm32h7_cfg_##n, \
221 &can_stm32h7_ops, \
222 &can_stm32h7_cbs_##n); \
223 \
224 static struct can_mcan_data can_mcan_data_##n = \
225 CAN_MCAN_DATA_INITIALIZER(NULL); \
226 \
227 CAN_DEVICE_DT_INST_DEFINE(n, can_stm32h7_init, NULL, \
228 &can_mcan_data_##n, \
229 &can_mcan_cfg_##n, \
230 POST_KERNEL, CONFIG_CAN_INIT_PRIORITY, \
231 &can_stm32h7_driver_api); \
232 \
233 static void stm32h7_mcan_irq_config_##n(void) \
234 { \
235 LOG_DBG("Enable CAN inst" #n " IRQ"); \
236 IRQ_CONNECT(DT_INST_IRQ_BY_NAME(n, line_0, irq), \
237 DT_INST_IRQ_BY_NAME(n, line_0, priority), \
238 can_mcan_line_0_isr, DEVICE_DT_INST_GET(n), 0); \
239 irq_enable(DT_INST_IRQ_BY_NAME(n, line_0, irq)); \
240 IRQ_CONNECT(DT_INST_IRQ_BY_NAME(n, line_1, irq), \
241 DT_INST_IRQ_BY_NAME(n, line_1, priority), \
242 can_mcan_line_1_isr, DEVICE_DT_INST_GET(n), 0); \
243 irq_enable(DT_INST_IRQ_BY_NAME(n, line_1, irq)); \
244 }
245
246 DT_INST_FOREACH_STATUS_OKAY(CAN_STM32H7_MCAN_INIT)
247
