1 /*
2 * Copyright (c) 2022 Vestas Wind Systems A/S
3 * Copyright (c) 2021 Alexander Wachter
4 * Copyright (c) 2022 Kamil Serwus
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 */
8
9 #include <zephyr/drivers/can.h>
10 #include <zephyr/drivers/can/can_mcan.h>
11 #include <zephyr/drivers/pinctrl.h>
12 #include <zephyr/irq.h>
13 #include <zephyr/kernel.h>
14 #include <zephyr/logging/log.h>
15 #include <soc.h>
16
17 LOG_MODULE_REGISTER(can_sam0, CONFIG_CAN_LOG_LEVEL);
18
19 #define DT_DRV_COMPAT atmel_sam0_can
20
21 struct can_sam0_config {
22 mm_reg_t base;
23 mem_addr_t mram;
24 void (*config_irq)(void);
25 const struct pinctrl_dev_config *pcfg;
26 volatile uint32_t *mclk;
27 uint32_t mclk_mask;
28 uint16_t gclk_core_id;
29 int divider;
30 };
31
can_sam0_read_reg(const struct device * dev,uint16_t reg,uint32_t * val)32 static int can_sam0_read_reg(const struct device *dev, uint16_t reg, uint32_t *val)
33 {
34 const struct can_mcan_config *mcan_config = dev->config;
35 const struct can_sam0_config *sam_config = mcan_config->custom;
36
37 return can_mcan_sys_read_reg(sam_config->base, reg, val);
38 }
39
can_sam0_write_reg(const struct device * dev,uint16_t reg,uint32_t val)40 static int can_sam0_write_reg(const struct device *dev, uint16_t reg, uint32_t val)
41 {
42 const struct can_mcan_config *mcan_config = dev->config;
43 const struct can_sam0_config *sam_config = mcan_config->custom;
44
45 switch (reg) {
46 case CAN_MCAN_ILS:
47 /* All interrupts are assigned to MCAN_INT0 */
48 val = 0;
49 break;
50 case CAN_MCAN_ILE:
51 /* SAM0 has only one line to handle interrupts */
52 val = CAN_MCAN_ILE_EINT0;
53 break;
54 default:
55 /* No field remap needed */
56 break;
57 };
58
59 return can_mcan_sys_write_reg(sam_config->base, reg, val);
60 }
61
can_sam0_read_mram(const struct device * dev,uint16_t offset,void * dst,size_t len)62 static int can_sam0_read_mram(const struct device *dev, uint16_t offset, void *dst, size_t len)
63 {
64 const struct can_mcan_config *mcan_config = dev->config;
65 const struct can_sam0_config *sam_config = mcan_config->custom;
66
67 return can_mcan_sys_read_mram(sam_config->mram, offset, dst, len);
68 }
69
can_sam0_write_mram(const struct device * dev,uint16_t offset,const void * src,size_t len)70 static int can_sam0_write_mram(const struct device *dev, uint16_t offset, const void *src,
71 size_t len)
72 {
73 const struct can_mcan_config *mcan_config = dev->config;
74 const struct can_sam0_config *sam_config = mcan_config->custom;
75
76 return can_mcan_sys_write_mram(sam_config->mram, offset, src, len);
77 }
78
can_sam0_clear_mram(const struct device * dev,uint16_t offset,size_t len)79 static int can_sam0_clear_mram(const struct device *dev, uint16_t offset, size_t len)
80 {
81 const struct can_mcan_config *mcan_config = dev->config;
82 const struct can_sam0_config *sam_config = mcan_config->custom;
83
84 return can_mcan_sys_clear_mram(sam_config->mram, offset, len);
85 }
86
can_sam0_line_x_isr(const struct device * dev)87 void can_sam0_line_x_isr(const struct device *dev)
88 {
89 can_mcan_line_0_isr(dev);
90 can_mcan_line_1_isr(dev);
91 }
92
can_sam0_get_core_clock(const struct device * dev,uint32_t * rate)93 static int can_sam0_get_core_clock(const struct device *dev, uint32_t *rate)
94 {
95 const struct can_mcan_config *mcan_cfg = dev->config;
96 const struct can_sam0_config *sam_cfg = mcan_cfg->custom;
97
98 *rate = SOC_ATMEL_SAM0_OSC48M_FREQ_HZ / (sam_cfg->divider);
99
100 return 0;
101 }
102
can_sam0_clock_enable(const struct can_sam0_config * cfg)103 static void can_sam0_clock_enable(const struct can_sam0_config *cfg)
104 {
105 /* Enable the GLCK7 with DIV*/
106 GCLK->GENCTRL[7].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_OSC48M)
107 | GCLK_GENCTRL_DIV(cfg->divider)
108 | GCLK_GENCTRL_GENEN;
109
110 /* Route channel */
111 GCLK->PCHCTRL[cfg->gclk_core_id].reg = GCLK_PCHCTRL_GEN_GCLK7
112 | GCLK_PCHCTRL_CHEN;
113
114 /* Enable CAN clock in MCLK */
115 *cfg->mclk |= cfg->mclk_mask;
116 }
117
can_sam0_init(const struct device * dev)118 static int can_sam0_init(const struct device *dev)
119 {
120 const struct can_mcan_config *mcan_cfg = dev->config;
121 const struct can_sam0_config *sam_cfg = mcan_cfg->custom;
122 int ret;
123
124 can_sam0_clock_enable(sam_cfg);
125
126 ret = pinctrl_apply_state(sam_cfg->pcfg, PINCTRL_STATE_DEFAULT);
127 if (ret < 0) {
128 LOG_ERR("failed to apply pinctrl");
129 return ret;
130 }
131
132 ret = can_mcan_configure_mram(dev, 0U, sam_cfg->mram);
133 if (ret != 0) {
134 LOG_ERR("failed to configure message ram");
135 return ret;
136 }
137
138 ret = can_mcan_init(dev);
139 if (ret != 0) {
140 LOG_ERR("failed to mcan init");
141 return ret;
142 }
143
144 sam_cfg->config_irq();
145
146 return ret;
147 }
148
149 static const struct can_driver_api can_sam0_driver_api = {
150 .get_capabilities = can_mcan_get_capabilities,
151 .start = can_mcan_start,
152 .stop = can_mcan_stop,
153 .set_mode = can_mcan_set_mode,
154 .set_timing = can_mcan_set_timing,
155 .send = can_mcan_send,
156 .add_rx_filter = can_mcan_add_rx_filter,
157 .remove_rx_filter = can_mcan_remove_rx_filter,
158 .get_state = can_mcan_get_state,
159 #ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY
160 .recover = can_mcan_recover,
161 #endif /* CONFIG_CAN_AUTO_BUS_OFF_RECOVERY */
162 .get_core_clock = can_sam0_get_core_clock,
163 .get_max_filters = can_mcan_get_max_filters,
164 .get_max_bitrate = can_mcan_get_max_bitrate,
165 .set_state_change_callback = can_mcan_set_state_change_callback,
166 .timing_min = CAN_MCAN_TIMING_MIN_INITIALIZER,
167 .timing_max = CAN_MCAN_TIMING_MAX_INITIALIZER,
168 #ifdef CONFIG_CAN_FD_MODE
169 .set_timing_data = can_mcan_set_timing_data,
170 .timing_data_min = CAN_MCAN_TIMING_DATA_MIN_INITIALIZER,
171 .timing_data_max = CAN_MCAN_TIMING_DATA_MAX_INITIALIZER,
172 #endif /* CONFIG_CAN_FD_MODE */
173 };
174
175 static const struct can_mcan_ops can_sam0_ops = {
176 .read_reg = can_sam0_read_reg,
177 .write_reg = can_sam0_write_reg,
178 .read_mram = can_sam0_read_mram,
179 .write_mram = can_sam0_write_mram,
180 .clear_mram = can_sam0_clear_mram,
181 };
182
183 #define CAN_SAM0_IRQ_CFG_FUNCTION(inst) \
184 static void config_can_##inst##_irq(void) \
185 { \
186 LOG_DBG("Enable CAN##inst## IRQ"); \
187 IRQ_CONNECT(DT_INST_IRQ_BY_NAME(inst, line_0, irq), \
188 DT_INST_IRQ_BY_NAME(inst, line_0, priority), can_sam0_line_x_isr, \
189 DEVICE_DT_INST_GET(inst), 0); \
190 irq_enable(DT_INST_IRQ_BY_NAME(inst, line_0, irq)); \
191 }
192
193 #define CAN_SAM0_CFG_INST(inst) \
194 CAN_MCAN_DT_INST_CALLBACKS_DEFINE(inst, can_sam0_cbs_##inst); \
195 CAN_MCAN_DT_INST_MRAM_DEFINE(inst, can_sam0_mram_##inst); \
196 \
197 static const struct can_sam0_config can_sam0_cfg_##inst = { \
198 .base = CAN_MCAN_DT_INST_MCAN_ADDR(inst), \
199 .mram = (mem_addr_t)POINTER_TO_UINT(&can_sam0_mram_##inst), \
200 .mclk = (volatile uint32_t *)MCLK_MASK_DT_INT_REG_ADDR(inst), \
201 .mclk_mask = BIT(DT_INST_CLOCKS_CELL_BY_NAME(inst, mclk, bit)), \
202 .gclk_core_id = DT_INST_CLOCKS_CELL_BY_NAME(inst, gclk, periph_ch), \
203 .divider = DT_INST_PROP(inst, divider), \
204 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
205 .config_irq = config_can_##inst##_irq, \
206 }; \
207 \
208 static const struct can_mcan_config can_mcan_cfg_##inst = \
209 CAN_MCAN_DT_CONFIG_INST_GET(inst, &can_sam0_cfg_##inst, &can_sam0_ops, \
210 &can_sam0_cbs_##inst);
211
212 #define CAN_SAM0_DATA_INST(inst) \
213 static struct can_mcan_data can_mcan_data_##inst = \
214 CAN_MCAN_DATA_INITIALIZER(NULL);
215
216 #define CAN_SAM0_DEVICE_INST(inst) \
217 CAN_DEVICE_DT_INST_DEFINE(inst, can_sam0_init, NULL, \
218 &can_mcan_data_##inst, \
219 &can_mcan_cfg_##inst, \
220 POST_KERNEL, CONFIG_CAN_INIT_PRIORITY, \
221 &can_sam0_driver_api);
222
223 #define CAN_SAM0_INST(inst) \
224 CAN_MCAN_DT_INST_BUILD_ASSERT_MRAM_CFG(inst); \
225 PINCTRL_DT_INST_DEFINE(inst); \
226 CAN_SAM0_IRQ_CFG_FUNCTION(inst) \
227 CAN_SAM0_CFG_INST(inst) \
228 CAN_SAM0_DATA_INST(inst) \
229 CAN_SAM0_DEVICE_INST(inst)
230
231 DT_INST_FOREACH_STATUS_OKAY(CAN_SAM0_INST)
232
