1 /*
2 * Copyright (c) 2022 Vestas Wind Systems A/S
3 * Copyright (c) 2021 Alexander Wachter
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #include <zephyr/drivers/can.h>
9 #include <zephyr/drivers/can/can_mcan.h>
10 #include <zephyr/drivers/pinctrl.h>
11 #include <zephyr/drivers/clock_control/atmel_sam_pmc.h>
12 #include <soc.h>
13 #include <zephyr/kernel.h>
14 #include <zephyr/logging/log.h>
15 #include <zephyr/irq.h>
16
17 LOG_MODULE_REGISTER(can_sam, CONFIG_CAN_LOG_LEVEL);
18
19 #define DT_DRV_COMPAT atmel_sam_can
20
21 struct can_sam_config {
22 mm_reg_t base;
23 mem_addr_t mram;
24 void (*config_irq)(void);
25 const struct atmel_sam_pmc_config clock_cfg;
26 const struct pinctrl_dev_config *pcfg;
27 int divider;
28 };
29
can_sam_read_reg(const struct device * dev,uint16_t reg,uint32_t * val)30 static int can_sam_read_reg(const struct device *dev, uint16_t reg, uint32_t *val)
31 {
32 const struct can_mcan_config *mcan_config = dev->config;
33 const struct can_sam_config *sam_config = mcan_config->custom;
34
35 return can_mcan_sys_read_reg(sam_config->base, reg, val);
36 }
37
can_sam_write_reg(const struct device * dev,uint16_t reg,uint32_t val)38 static int can_sam_write_reg(const struct device *dev, uint16_t reg, uint32_t val)
39 {
40 const struct can_mcan_config *mcan_config = dev->config;
41 const struct can_sam_config *sam_config = mcan_config->custom;
42
43 return can_mcan_sys_write_reg(sam_config->base, reg, val);
44 }
45
can_sam_read_mram(const struct device * dev,uint16_t offset,void * dst,size_t len)46 static int can_sam_read_mram(const struct device *dev, uint16_t offset, void *dst, size_t len)
47 {
48 const struct can_mcan_config *mcan_config = dev->config;
49 const struct can_sam_config *sam_config = mcan_config->custom;
50
51 return can_mcan_sys_read_mram(sam_config->mram, offset, dst, len);
52 }
53
can_sam_write_mram(const struct device * dev,uint16_t offset,const void * src,size_t len)54 static int can_sam_write_mram(const struct device *dev, uint16_t offset, const void *src,
55 size_t len)
56 {
57 const struct can_mcan_config *mcan_config = dev->config;
58 const struct can_sam_config *sam_config = mcan_config->custom;
59
60 return can_mcan_sys_write_mram(sam_config->mram, offset, src, len);
61 }
62
can_sam_clear_mram(const struct device * dev,uint16_t offset,size_t len)63 static int can_sam_clear_mram(const struct device *dev, uint16_t offset, size_t len)
64 {
65 const struct can_mcan_config *mcan_config = dev->config;
66 const struct can_sam_config *sam_config = mcan_config->custom;
67
68 return can_mcan_sys_clear_mram(sam_config->mram, offset, len);
69 }
70
can_sam_get_core_clock(const struct device * dev,uint32_t * rate)71 static int can_sam_get_core_clock(const struct device *dev, uint32_t *rate)
72 {
73 const struct can_mcan_config *mcan_cfg = dev->config;
74 const struct can_sam_config *sam_cfg = mcan_cfg->custom;
75
76 *rate = SOC_ATMEL_SAM_UPLLCK_FREQ_HZ / (sam_cfg->divider);
77
78 return 0;
79 }
80
can_sam_clock_enable(const struct can_sam_config * sam_cfg)81 static void can_sam_clock_enable(const struct can_sam_config *sam_cfg)
82 {
83 REG_PMC_PCK5 = PMC_PCK_CSS_UPLL_CLK | PMC_PCK_PRES(sam_cfg->divider - 1);
84 PMC->PMC_SCER |= PMC_SCER_PCK5;
85
86 /* Enable CAN clock in PMC */
87 (void)clock_control_on(SAM_DT_PMC_CONTROLLER,
88 (clock_control_subsys_t)&sam_cfg->clock_cfg);
89 }
90
can_sam_init(const struct device * dev)91 static int can_sam_init(const struct device *dev)
92 {
93 const struct can_mcan_config *mcan_cfg = dev->config;
94 const struct can_sam_config *sam_cfg = mcan_cfg->custom;
95 int ret;
96
97 can_sam_clock_enable(sam_cfg);
98
99 ret = pinctrl_apply_state(sam_cfg->pcfg, PINCTRL_STATE_DEFAULT);
100 if (ret < 0) {
101 return ret;
102 }
103
104 ret = can_mcan_configure_mram(dev, 0U, sam_cfg->mram);
105 if (ret != 0) {
106 return ret;
107 }
108
109 ret = can_mcan_init(dev);
110 if (ret != 0) {
111 return ret;
112 }
113
114 sam_cfg->config_irq();
115
116 return ret;
117 }
118
119 static const struct can_driver_api can_sam_driver_api = {
120 .get_capabilities = can_mcan_get_capabilities,
121 .start = can_mcan_start,
122 .stop = can_mcan_stop,
123 .set_mode = can_mcan_set_mode,
124 .set_timing = can_mcan_set_timing,
125 .send = can_mcan_send,
126 .add_rx_filter = can_mcan_add_rx_filter,
127 .remove_rx_filter = can_mcan_remove_rx_filter,
128 .get_state = can_mcan_get_state,
129 #ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY
130 .recover = can_mcan_recover,
131 #endif /* CONFIG_CAN_AUTO_BUS_OFF_RECOVERY */
132 .get_core_clock = can_sam_get_core_clock,
133 .get_max_filters = can_mcan_get_max_filters,
134 .get_max_bitrate = can_mcan_get_max_bitrate,
135 .set_state_change_callback = can_mcan_set_state_change_callback,
136 .timing_min = CAN_MCAN_TIMING_MIN_INITIALIZER,
137 .timing_max = CAN_MCAN_TIMING_MAX_INITIALIZER,
138 #ifdef CONFIG_CAN_FD_MODE
139 .set_timing_data = can_mcan_set_timing_data,
140 .timing_data_min = CAN_MCAN_TIMING_DATA_MIN_INITIALIZER,
141 .timing_data_max = CAN_MCAN_TIMING_DATA_MAX_INITIALIZER,
142 #endif /* CONFIG_CAN_FD_MODE */
143 };
144
145 static const struct can_mcan_ops can_sam_ops = {
146 .read_reg = can_sam_read_reg,
147 .write_reg = can_sam_write_reg,
148 .read_mram = can_sam_read_mram,
149 .write_mram = can_sam_write_mram,
150 .clear_mram = can_sam_clear_mram,
151 };
152
153 #define CAN_SAM_IRQ_CFG_FUNCTION(inst) \
154 static void config_can_##inst##_irq(void) \
155 { \
156 LOG_DBG("Enable CAN##inst## IRQ"); \
157 IRQ_CONNECT(DT_INST_IRQ_BY_NAME(inst, line_0, irq), \
158 DT_INST_IRQ_BY_NAME(inst, line_0, priority), can_mcan_line_0_isr, \
159 DEVICE_DT_INST_GET(inst), 0); \
160 irq_enable(DT_INST_IRQ_BY_NAME(inst, line_0, irq)); \
161 IRQ_CONNECT(DT_INST_IRQ_BY_NAME(inst, line_1, irq), \
162 DT_INST_IRQ_BY_NAME(inst, line_1, priority), can_mcan_line_1_isr, \
163 DEVICE_DT_INST_GET(inst), 0); \
164 irq_enable(DT_INST_IRQ_BY_NAME(inst, line_1, irq)); \
165 }
166
167 #define CAN_SAM_CFG_INST(inst) \
168 CAN_MCAN_DT_INST_CALLBACKS_DEFINE(inst, can_sam_cbs_##inst); \
169 CAN_MCAN_DT_INST_MRAM_DEFINE(inst, can_sam_mram_##inst); \
170 \
171 static const struct can_sam_config can_sam_cfg_##inst = { \
172 .base = CAN_MCAN_DT_INST_MCAN_ADDR(inst), \
173 .mram = (mem_addr_t)POINTER_TO_UINT(&can_sam_mram_##inst), \
174 .clock_cfg = SAM_DT_INST_CLOCK_PMC_CFG(inst), \
175 .divider = DT_INST_PROP(inst, divider), \
176 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
177 .config_irq = config_can_##inst##_irq, \
178 }; \
179 \
180 static const struct can_mcan_config can_mcan_cfg_##inst = \
181 CAN_MCAN_DT_CONFIG_INST_GET(inst, &can_sam_cfg_##inst, \
182 &can_sam_ops, \
183 &can_sam_cbs_##inst);
184
185 #define CAN_SAM_DATA_INST(inst) \
186 static struct can_mcan_data can_mcan_data_##inst = \
187 CAN_MCAN_DATA_INITIALIZER(NULL);
188
189 #define CAN_SAM_DEVICE_INST(inst) \
190 CAN_DEVICE_DT_INST_DEFINE(inst, can_sam_init, NULL, \
191 &can_mcan_data_##inst, \
192 &can_mcan_cfg_##inst, \
193 POST_KERNEL, CONFIG_CAN_INIT_PRIORITY, \
194 &can_sam_driver_api);
195
196 #define CAN_SAM_INST(inst) \
197 CAN_MCAN_DT_INST_BUILD_ASSERT_MRAM_CFG(inst); \
198 PINCTRL_DT_INST_DEFINE(inst); \
199 CAN_SAM_IRQ_CFG_FUNCTION(inst) \
200 CAN_SAM_CFG_INST(inst) \
201 CAN_SAM_DATA_INST(inst) \
202 CAN_SAM_DEVICE_INST(inst)
203
204 DT_INST_FOREACH_STATUS_OKAY(CAN_SAM_INST)
205
