1 /*
2 * Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <zephyr/device.h>
8 #include <zephyr/drivers/can.h>
9 #include <zephyr/drivers/can/can_mcan.h>
10 #include <zephyr/drivers/clock_control.h>
11 #include <zephyr/drivers/pinctrl.h>
12 #include <zephyr/logging/log.h>
13 #include <zephyr/irq.h>
14
15 LOG_MODULE_REGISTER(can_mcux_mcan, CONFIG_CAN_LOG_LEVEL);
16
17 #define DT_DRV_COMPAT nxp_lpc_mcan
18
19 /* Message RAM Base Address register */
20 #define MCUX_MCAN_MRBA 0x200
21 #define MCUX_MCAN_MRBA_BA GENMASK(31, 16)
22
23 struct mcux_mcan_config {
24 mm_reg_t base;
25 mem_addr_t mram;
26 const struct device *clock_dev;
27 clock_control_subsys_t clock_subsys;
28 void (*irq_config_func)(const struct device *dev);
29 const struct pinctrl_dev_config *pincfg;
30 };
31
mcux_mcan_read_reg(const struct device * dev,uint16_t reg,uint32_t * val)32 static int mcux_mcan_read_reg(const struct device *dev, uint16_t reg, uint32_t *val)
33 {
34 const struct can_mcan_config *mcan_config = dev->config;
35 const struct mcux_mcan_config *mcux_config = mcan_config->custom;
36
37 return can_mcan_sys_read_reg(mcux_config->base, reg, val);
38 }
39
mcux_mcan_write_reg(const struct device * dev,uint16_t reg,uint32_t val)40 static int mcux_mcan_write_reg(const struct device *dev, uint16_t reg, uint32_t val)
41 {
42 const struct can_mcan_config *mcan_config = dev->config;
43 const struct mcux_mcan_config *mcux_config = mcan_config->custom;
44
45 return can_mcan_sys_write_reg(mcux_config->base, reg, val);
46 }
47
mcux_mcan_read_mram(const struct device * dev,uint16_t offset,void * dst,size_t len)48 static int mcux_mcan_read_mram(const struct device *dev, uint16_t offset, void *dst, size_t len)
49 {
50 const struct can_mcan_config *mcan_config = dev->config;
51 const struct mcux_mcan_config *mcux_config = mcan_config->custom;
52
53 return can_mcan_sys_read_mram(mcux_config->mram, offset, dst, len);
54 }
55
mcux_mcan_write_mram(const struct device * dev,uint16_t offset,const void * src,size_t len)56 static int mcux_mcan_write_mram(const struct device *dev, uint16_t offset, const void *src,
57 size_t len)
58 {
59 const struct can_mcan_config *mcan_config = dev->config;
60 const struct mcux_mcan_config *mcux_config = mcan_config->custom;
61
62 return can_mcan_sys_write_mram(mcux_config->mram, offset, src, len);
63 }
64
mcux_mcan_clear_mram(const struct device * dev,uint16_t offset,size_t len)65 static int mcux_mcan_clear_mram(const struct device *dev, uint16_t offset, size_t len)
66 {
67 const struct can_mcan_config *mcan_config = dev->config;
68 const struct mcux_mcan_config *mcux_config = mcan_config->custom;
69
70 return can_mcan_sys_clear_mram(mcux_config->mram, offset, len);
71 }
72
mcux_mcan_get_core_clock(const struct device * dev,uint32_t * rate)73 static int mcux_mcan_get_core_clock(const struct device *dev, uint32_t *rate)
74 {
75 const struct can_mcan_config *mcan_config = dev->config;
76 const struct mcux_mcan_config *mcux_config = mcan_config->custom;
77
78 return clock_control_get_rate(mcux_config->clock_dev, mcux_config->clock_subsys,
79 rate);
80 }
81
mcux_mcan_init(const struct device * dev)82 static int mcux_mcan_init(const struct device *dev)
83 {
84 const struct can_mcan_config *mcan_config = dev->config;
85 const struct mcux_mcan_config *mcux_config = mcan_config->custom;
86 const uintptr_t mrba = mcux_config->mram & MCUX_MCAN_MRBA_BA;
87 int err;
88
89 if (!device_is_ready(mcux_config->clock_dev)) {
90 LOG_ERR("clock control device not ready");
91 return -ENODEV;
92 }
93
94 err = pinctrl_apply_state(mcux_config->pincfg, PINCTRL_STATE_DEFAULT);
95 if (err) {
96 return err;
97 }
98
99 err = clock_control_on(mcux_config->clock_dev, mcux_config->clock_subsys);
100 if (err) {
101 LOG_ERR("failed to enable clock (err %d)", err);
102 return -EINVAL;
103 }
104
105 err = can_mcan_write_reg(dev, MCUX_MCAN_MRBA, (uint32_t)mrba);
106 if (err != 0) {
107 return -EIO;
108 }
109
110 err = can_mcan_configure_mram(dev, mrba, mcux_config->mram);
111 if (err != 0) {
112 return -EIO;
113 }
114
115 err = can_mcan_init(dev);
116 if (err) {
117 LOG_ERR("failed to initialize mcan (err %d)", err);
118 return err;
119 }
120
121 mcux_config->irq_config_func(dev);
122
123 return 0;
124 }
125
126 static const struct can_driver_api mcux_mcan_driver_api = {
127 .get_capabilities = can_mcan_get_capabilities,
128 .start = can_mcan_start,
129 .stop = can_mcan_stop,
130 .set_mode = can_mcan_set_mode,
131 .set_timing = can_mcan_set_timing,
132 .send = can_mcan_send,
133 .add_rx_filter = can_mcan_add_rx_filter,
134 .remove_rx_filter = can_mcan_remove_rx_filter,
135 #ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY
136 .recover = can_mcan_recover,
137 #endif /* CONFIG_CAN_AUTO_BUS_OFF_RECOVERY */
138 .get_state = can_mcan_get_state,
139 .set_state_change_callback = can_mcan_set_state_change_callback,
140 .get_core_clock = mcux_mcan_get_core_clock,
141 .get_max_filters = can_mcan_get_max_filters,
142 .get_max_bitrate = can_mcan_get_max_bitrate,
143 /*
144 * MCUX MCAN timing limits are specified in the "Nominal bit timing and
145 * prescaler register (NBTP)" table in the SoC reference manual.
146 *
147 * Note that the values here are the "physical" timing limits, whereas
148 * the register field limits are physical values minus 1 (which is
149 * handled by the register assignments in the common MCAN driver code).
150 *
151 * Beware that at least some SoC reference manuals contain a bug
152 * regarding the minimum values for nominal phase segments. Valid
153 * register values are 1 and up.
154 */
155 .timing_min = CAN_MCAN_TIMING_MIN_INITIALIZER,
156 .timing_max = CAN_MCAN_TIMING_MAX_INITIALIZER,
157 #ifdef CONFIG_CAN_FD_MODE
158 .set_timing_data = can_mcan_set_timing_data,
159 /*
160 * MCUX MCAN data timing limits are specified in the "Data bit timing
161 * and prescaler register (DBTP)" table in the SoC reference manual.
162 *
163 * Note that the values here are the "physical" timing limits, whereas
164 * the register field limits are physical values minus 1 (which is
165 * handled by the register assignments in the common MCAN driver code).
166 *
167 * Beware that at least some SoC reference manuals contain a bug
168 * regarding the maximum value for data phase segment 2. Valid register
169 * values are 0 to 31.
170 */
171 .timing_data_min = CAN_MCAN_TIMING_DATA_MIN_INITIALIZER,
172 .timing_data_max = CAN_MCAN_TIMING_DATA_MAX_INITIALIZER,
173 #endif /* CONFIG_CAN_FD_MODE */
174 };
175
176 static const struct can_mcan_ops mcux_mcan_ops = {
177 .read_reg = mcux_mcan_read_reg,
178 .write_reg = mcux_mcan_write_reg,
179 .read_mram = mcux_mcan_read_mram,
180 .write_mram = mcux_mcan_write_mram,
181 .clear_mram = mcux_mcan_clear_mram,
182 };
183
184 #define MCUX_MCAN_INIT(n) \
185 CAN_MCAN_DT_INST_BUILD_ASSERT_MRAM_CFG(n); \
186 PINCTRL_DT_INST_DEFINE(n); \
187 \
188 static void mcux_mcan_irq_config_##n(const struct device *dev); \
189 \
190 CAN_MCAN_DT_INST_CALLBACKS_DEFINE(n, mcux_mcan_cbs_##n); \
191 CAN_MCAN_DT_INST_MRAM_DEFINE(n, mcux_mcan_mram_##n); \
192 \
193 static const struct mcux_mcan_config mcux_mcan_config_##n = { \
194 .base = CAN_MCAN_DT_INST_MCAN_ADDR(n), \
195 .mram = (mem_addr_t)POINTER_TO_UINT(&mcux_mcan_mram_##n), \
196 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
197 .clock_subsys = (clock_control_subsys_t) \
198 DT_INST_CLOCKS_CELL(n, name), \
199 .irq_config_func = mcux_mcan_irq_config_##n, \
200 .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
201 }; \
202 \
203 static const struct can_mcan_config can_mcan_config_##n = \
204 CAN_MCAN_DT_CONFIG_INST_GET(n, &mcux_mcan_config_##n, \
205 &mcux_mcan_ops, \
206 &mcux_mcan_cbs_##n); \
207 \
208 static struct can_mcan_data can_mcan_data_##n = \
209 CAN_MCAN_DATA_INITIALIZER(NULL); \
210 \
211 CAN_DEVICE_DT_INST_DEFINE(n, mcux_mcan_init, NULL, \
212 &can_mcan_data_##n, \
213 &can_mcan_config_##n, \
214 POST_KERNEL, \
215 CONFIG_CAN_INIT_PRIORITY, \
216 &mcux_mcan_driver_api); \
217 \
218 static void mcux_mcan_irq_config_##n(const struct device *dev) \
219 { \
220 IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, 0, irq), \
221 DT_INST_IRQ_BY_IDX(n, 0, priority), \
222 can_mcan_line_0_isr, \
223 DEVICE_DT_INST_GET(n), 0); \
224 irq_enable(DT_INST_IRQ_BY_IDX(n, 0, irq)); \
225 \
226 IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, 1, irq), \
227 DT_INST_IRQ_BY_IDX(n, 1, priority), \
228 can_mcan_line_1_isr, \
229 DEVICE_DT_INST_GET(n), 0); \
230 irq_enable(DT_INST_IRQ_BY_IDX(n, 1, irq)); \
231 }
232
233 DT_INST_FOREACH_STATUS_OKAY(MCUX_MCAN_INIT)
234
