1/*
2 * Copyright 2024 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <zephyr/dt-bindings/mipi_dbi/mipi_dbi.h>
8
9/*
10 * To use this board with this display, perform the following modifications:
11 * - Depopulate resistors R78, R604, R598, R15, R245, R243, R11, R20, R237,
12 *   R235, R431, R447, R420, R459, R485, and R486
13 * - Populate resistors R286, R19, R246, R242, R123, R239, R124, R125, R236,
14 *   R233, and R12
15 * - Remove jumper JP30
16 * - Set jumper JP40 to postion 1-2, JP38 to 1-2, and JP16 to position 2-3
17 */
18
19/*
20 * To connect the display configure SW1 on the display to
21 * ON-ON-OFF (8 bit 8080 mode), and connect the following pins
22 * | Board Pin | Display Pin | Function |
23 * |-----------|-------------|----------|
24 * | HD2.8     | D0          | D[0]     |
25 * | HD2.16    | D1          | D[1]     |
26 * | J5.2      | TE          | TE       |
27 * | J5.4      | D2          | D[2]     |
28 * | J5.1      | D3          | D[3]     |
29 * | J5.6      | RD          | RDX      |
30 * | J5.3      | D4          | D[4]     |
31 * | HD2.7     | D5          | D[5]     |
32 * | HD2.6     | D6          | D[6]     |
33 * | HD2.1     | D7          | D[7]     |
34 * | HD2.2     | WR          | WR       |
35 * | HD8.1     | CS          | CS       |
36 * | HD8.2     | D/C         | DC       |
37 * | J13.8     | GND         | GND      |
38 * | J13.7     | VDD         | 3V3      |
39 * | J5.10     | SCL         | IC2_SCL  |
40 * | J5.9      | SDA         | IC2_SDA  |
41 * | HD2.4     | INT         | INT      |
42 * | HD2.5     | RST         | RESET    |
43 */
44
45/* Expand the LCDIC pinmux to cover all 8080 mode pins */
46&pinmux_lcdic {
47	group0 {
48		pinmux = <IO_MUX_LCD_8080_IO42>,
49			<IO_MUX_LCD_8080_IO43>,
50			<IO_MUX_LCD_8080_IO44>,
51			<IO_MUX_LCD_8080_IO45>,
52			<IO_MUX_LCD_8080_IO46>,
53			<IO_MUX_LCD_8080_IO47>,
54			<IO_MUX_LCD_8080_IO48>,
55			<IO_MUX_LCD_8080_IO49>,
56			<IO_MUX_LCD_8080_IO51>,
57			<IO_MUX_LCD_8080_IO52>,
58			<IO_MUX_LCD_8080_IO53>,
59			<IO_MUX_LCD_8080_IO54>,
60			<IO_MUX_LCD_8080_IO56>,
61			<IO_MUX_LCD_8080_IO57>;
62		slew-rate = "ultra";
63	};
64};
65
66&st7796s {
67	mipi-mode = "MIPI_DBI_MODE_8080_BUS_8_BIT";
68	/*
69	 * Display supports minimum write cycle time of 66ns. This
70	 * means we can clock the LCDIC module at 30MHz, as
71	 * the minimum write duration will be 2x the module
72	 * clock. Note that this frequency is too fast for reading
73	 * from the display module
74	 */
75	mipi-max-frequency = <30000000>;
76	/*
77	 * Note that this display is *not* buggy- we use rgb-is-inverted
78	 * as a workaround here to get the display to report an inverted
79	 * color format. This is because the "nxp,swap-bytes" setting
80	 * on the LCDIC will apply byte swapping in hardware, so the
81	 * display should report an inverted color format to account
82	 * for this. This results in better performance for applications
83	 * like LVGL, which would otherwise have to swap RGB565 data in
84	 * software
85	 */
86	rgb-is-inverted;
87	/* Enable TE synchronization, using the rising edge */
88	te-mode = "MIPI_DBI_TE_RISING_EDGE";
89};
90
91&lcdic {
92	/* Enable byte swapping */
93	nxp,swap-bytes;
94	/* Set pulse width for write active and write inactive to min value */
95	nxp,write-active-cycles = <1>;
96	nxp,write-inactive-cycles = <1>;
97	/* Raise the timer0 ratio to enable longer reset delay */
98	nxp,timer0-ratio = <15>;
99	/* Lower timer1 ratio to enable shorter TE delay */
100	nxp,timer1-ratio = <0>;
101};
102