1/*
2 * Copyright (c) 2019 Laird Connectivity
3 * Copyright (c) 2023 Nordic Semiconductor ASA
4 * Copyright (c) 2024 Ezurio
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 */
8
9/dts-v1/;
10#include <nordic/nrf52832_qfaa.dtsi>
11#include "bl652_dvk-pinctrl.dtsi"
12#include <zephyr/dt-bindings/input/input-event-codes.h>
13
14/ {
15	model = "Ezurio BL652 DVK";
16	compatible = "ezurio,bl652_dvk";
17
18	chosen {
19		zephyr,console = &uart0;
20		zephyr,shell-uart = &uart0;
21		zephyr,uart-mcumgr = &uart0;
22		zephyr,bt-mon-uart = &uart0;
23		zephyr,bt-c2h-uart = &uart0;
24		zephyr,sram = &sram0;
25		zephyr,flash = &flash0;
26		zephyr,code-partition = &slot0_partition;
27	};
28
29	leds {
30		compatible = "gpio-leds";
31		led1: led_1 {
32			gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
33			label = "Blue LED 1";
34		};
35		led2: led_2 {
36			gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
37			label = "Blue LED 2";
38		};
39	};
40
41	buttons {
42		compatible = "gpio-keys";
43		button1: button_1 {
44			gpios = <&gpio0 11 GPIO_PULL_UP>;
45			label = "Push button switch 1";
46			zephyr,code = <INPUT_KEY_0>;
47		};
48		button2: button_2 {
49			gpios = <&gpio0 15 GPIO_PULL_UP>;
50			label = "Push button switch 2";
51			zephyr,code = <INPUT_KEY_1>;
52		};
53	};
54
55	/* These aliases are provided for compatibility with samples */
56	aliases {
57		led0 = &led1;
58		led1 = &led2;
59		sw0 = &button1;
60		sw1 = &button2;
61		mcuboot-button0 = &button1;
62		mcuboot-led0 = &led1;
63		watchdog0 = &wdt0;
64		bbram0 = &extrtc0;
65	};
66};
67
68&reg {
69	regulator-initial-mode = <NRF5X_REG_MODE_DCDC>;
70};
71
72&adc {
73	status = "okay";
74};
75
76&uicr {
77	gpio-as-nreset;
78};
79
80&gpiote {
81	status = "okay";
82};
83
84&gpio0 {
85	status = "okay";
86};
87
88&uart0 {
89	status = "okay";
90	compatible = "nordic,nrf-uart";
91	current-speed = <115200>;
92	pinctrl-0 = <&uart0_default>;
93	pinctrl-1 = <&uart0_sleep>;
94	pinctrl-names = "default", "sleep";
95};
96
97&i2c0 {
98	compatible = "nordic,nrf-twi";
99	status = "okay";
100
101	pinctrl-0 = <&i2c0_default>;
102	pinctrl-1 = <&i2c0_sleep>;
103	pinctrl-names = "default", "sleep";
104	dac0: mcp4725@60 {
105		/* MCP4725 not populated at factory */
106		compatible = "microchip,mcp4725";
107		reg = <0x60>;
108		#io-channel-cells = <1>;
109		status = "disabled";
110	};
111
112	extrtc0: mcp7940n@6f {
113		compatible = "microchip,mcp7940n";
114		reg = <0x6f>;
115		status = "okay";
116	};
117};
118
119&pwm0 {
120	status = "okay";
121	pinctrl-0 = <&pwm0_default>;
122	pinctrl-1 = <&pwm0_sleep>;
123	pinctrl-names = "default", "sleep";
124};
125
126&spi0 {
127	compatible = "nordic,nrf-spi";
128	/* Cannot be used together with i2c0. */
129	/* status = "okay"; */
130	cs-gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
131	pinctrl-0 = <&spi0_default>;
132	pinctrl-1 = <&spi0_sleep>;
133	pinctrl-names = "default", "sleep";
134};
135
136&spi1 {
137	compatible = "nordic,nrf-spi";
138	status = "okay";
139	cs-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
140	pinctrl-0 = <&spi1_default>;
141	pinctrl-1 = <&spi1_sleep>;
142	pinctrl-names = "default", "sleep";
143};
144
145&flash0 {
146
147	partitions {
148		compatible = "fixed-partitions";
149		#address-cells = <1>;
150		#size-cells = <1>;
151
152		boot_partition: partition@0 {
153			label = "mcuboot";
154			reg = <0x00000000 0xc000>;
155		};
156		slot0_partition: partition@c000 {
157			label = "image-0";
158			reg = <0x0000C000 0x32000>;
159		};
160		slot1_partition: partition@3e000 {
161			label = "image-1";
162			reg = <0x0003E000 0x32000>;
163		};
164		scratch_partition: partition@70000 {
165			label = "image-scratch";
166			reg = <0x00070000 0xa000>;
167		};
168		storage_partition: partition@7a000 {
169			label = "storage";
170			reg = <0x0007a000 0x00006000>;
171		};
172	};
173};
174