1/*
2 * Copyright (c) 2019-2020 Nordic Semiconductor ASA
3 * Copyright (c) 2021 Laird Connectivity
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8/*
9 * Default Flash planning for bl5340_dvk CPUAPP (Application MCU).
10 *
11 * Zephyr build for BL5340 with ARM TrustZone-M support
12 * implies building Secure and Non-Secure Zephyr images.
13 *
14 * Secure image will be placed, by default, in flash0
15 * (or in slot0, if MCUboot is present).
16 * Secure image will use sram0 for system memory.
17 *
18 * Non-Secure image will be placed in slot0_ns, and use
19 * sram0_ns for system memory.
20 *
21 * Note that the Secure image only requires knowledge of
22 * the beginning of the Non-Secure image (not its size).
23 */
24
25&slot0_partition {
26	reg = <0x00010000 0xa0000>;
27};
28
29&slot0_ns_partition {
30	reg = <0x000b0000 0x40000>;
31};
32
33&slot1_partition {
34	reg = <0x00000000 0xa0000>;
35};
36
37&slot1_ns_partition {
38	reg = <0x000a0000 0x40000>;
39};
40
41/* Default SRAM planning when building for nRF5340 with
42 * ARM TrustZone-M support
43 * - Lowest 256 kB SRAM allocated to Secure image (sram0_s)
44 * - Middle 192 kB allocated to Non-Secure image (sram0_ns)
45 * - Upper 64 kB SRAM allocated as Shared memory (sram0_shared)
46 *   (see bl5340_dvk_shared_sram_planning_conf.dtsi)
47 */
48&sram0_image {
49	reg = <0x20000000 DT_SIZE_K(448)>;
50};
51
52&sram0_s {
53	reg = <0x20000000 0x40000>;
54};
55
56&sram0_ns {
57	reg = <0x20040000 0x30000>;
58};
59
60/* Include default shared RAM configuration file */
61#include <common/nordic/nrf5340_shared_sram_partition.dtsi>
62