1/*
2 * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <common/bl_common.ld.h>
8#include <lib/xlat_tables/xlat_tables_defs.h>
9
10OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
11OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
12ENTRY(tsp_entrypoint)
13
14MEMORY {
15    RAM (rwx): ORIGIN = TSP_SEC_MEM_BASE, LENGTH = TSP_SEC_MEM_SIZE
16}
17
18SECTIONS {
19    RAM_REGION_START = ORIGIN(RAM);
20    RAM_REGION_LENGTH = LENGTH(RAM);
21    . = BL32_BASE;
22
23    ASSERT(. == ALIGN(PAGE_SIZE),
24        "BL32_BASE address is not aligned on a page boundary.")
25
26#if SEPARATE_CODE_AND_RODATA
27    .text . : {
28        __TEXT_START__ = .;
29
30        *tsp_entrypoint.o(.text*)
31        *(.text*)
32        *(.vectors)
33        __TEXT_END_UNALIGNED__ = .;
34
35        . = ALIGN(PAGE_SIZE);
36
37        __TEXT_END__ = .;
38    } >RAM
39
40    .rodata . : {
41        __RODATA_START__ = .;
42
43        *(.rodata*)
44
45        RODATA_COMMON
46
47        __RODATA_END_UNALIGNED__ = .;
48        . = ALIGN(PAGE_SIZE);
49
50        __RODATA_END__ = .;
51    } >RAM
52#else /* SEPARATE_CODE_AND_RODATA */
53    .ro . : {
54        __RO_START__ = .;
55
56        *tsp_entrypoint.o(.text*)
57        *(.text*)
58        *(.rodata*)
59
60        RODATA_COMMON
61
62        *(.vectors)
63
64        __RO_END_UNALIGNED__ = .;
65
66        /*
67         * Memory page(s) mapped to this section will be marked as read-only,
68         * executable. No RW data from the next section must creep in. Ensure
69         * that the rest of the current memory page is unused.
70         */
71        . = ALIGN(PAGE_SIZE);
72
73        __RO_END__ = .;
74    } >RAM
75#endif /* SEPARATE_CODE_AND_RODATA */
76
77    __RW_START__ = .;
78
79    DATA_SECTION >RAM
80    RELA_SECTION >RAM
81
82#ifdef TSP_PROGBITS_LIMIT
83    ASSERT(. <= TSP_PROGBITS_LIMIT, "TSP progbits has exceeded its limit.")
84#endif /* TSP_PROGBITS_LIMIT */
85
86    STACK_SECTION >RAM
87    BSS_SECTION >RAM
88    XLAT_TABLE_SECTION >RAM
89
90#if USE_COHERENT_MEM
91    /*
92     * The base address of the coherent memory section must be page-aligned to
93     * guarantee that the coherent data are stored on their own pages and are
94     * not mixed with normal data. This is required to set up the correct memory
95     * attributes for the coherent data page tables.
96     */
97    .coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
98        __COHERENT_RAM_START__ = .;
99        *(.tzfw_coherent_mem)
100        __COHERENT_RAM_END_UNALIGNED__ = .;
101
102        /*
103         * Memory page(s) mapped to this section will be marked as device
104         * memory. No other unexpected data must creep in. Ensure that the rest
105         * of the current memory page is unused.
106         */
107        . = ALIGN(PAGE_SIZE);
108
109        __COHERENT_RAM_END__ = .;
110    } >RAM
111#endif /* USE_COHERENT_MEM */
112
113    __RW_END__ = .;
114    __BL32_END__ = .;
115
116    /DISCARD/ : {
117        *(.dynsym .dynstr .hash .gnu.hash)
118    }
119
120    __BSS_SIZE__ = SIZEOF(.bss);
121
122#if USE_COHERENT_MEM
123    __COHERENT_RAM_UNALIGNED_SIZE__ =
124        __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
125#endif /* USE_COHERENT_MEM */
126
127    ASSERT(. <= BL32_LIMIT, "BL32 image has exceeded its limit.")
128    RAM_REGION_END = .;
129}
130