1/*
2 * Copyright (c) 2017 Google LLC.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <arm/armv6-m.dtsi>
9#include <zephyr/dt-bindings/adc/adc.h>
10#include <zephyr/dt-bindings/gpio/gpio.h>
11#include <zephyr/dt-bindings/i2c/i2c.h>
12#include <zephyr/dt-bindings/pwm/pwm.h>
13
14/ {
15	aliases {
16		watchdog0 = &wdog;
17	};
18
19	chosen {
20		zephyr,flash-controller = &nvmctrl;
21	};
22
23	cpus {
24		#address-cells = <1>;
25		#size-cells = <0>;
26
27		cpu0: cpu@0 {
28			device_type = "cpu";
29			compatible = "arm,cortex-m0+";
30			reg = <0>;
31		};
32	};
33
34	sram0: memory@20000000 {
35		compatible = "mmio-sram";
36	};
37
38	id: device_id@80a00c {
39		compatible = "atmel,sam0-id";
40		reg =	<0x0080A00C 0x4>,
41			<0x0080A040 0x4>,
42			<0x0080A044 0x4>,
43			<0x0080A048 0x4>;
44	};
45
46	aliases {
47		port-a = &porta;
48		port-b = &portb;
49		adc-0 = &adc;
50
51		sercom-0 = &sercom0;
52		sercom-1 = &sercom1;
53		sercom-2 = &sercom2;
54		sercom-3 = &sercom3;
55		sercom-4 = &sercom4;
56		sercom-5 = &sercom5;
57
58		tc-4 = &tc4;
59	};
60
61	soc {
62		nvmctrl: nvmctrl@41004000  {
63			compatible = "atmel,sam0-nvmctrl";
64			reg = <0x41004000 0x22>;
65			interrupts = <5 0>;
66			lock-regions = <16>;
67
68			#address-cells = <1>;
69			#size-cells = <1>;
70
71			flash0: flash@0 {
72				compatible = "soc-nv-flash";
73				write-block-size = <4>;
74			};
75		};
76
77		pm: pm@40000400 {
78			compatible = "atmel,samd2x-pm";
79			reg = <0x40000400 0x400>;
80			interrupts = <0 0>;
81			#clock-cells = <2>;
82		};
83
84		gclk: gclk@40000c00 {
85			compatible = "atmel,samd2x-gclk";
86			reg = <0x40000c00 0x400>;
87			#clock-cells = <1>;
88		};
89
90		eic: eic@40001800 {
91			compatible = "atmel,sam0-eic";
92			reg = <0x40001800 0x1C>;
93			interrupts = <4 0>;
94		};
95
96		pinmux_a: pinmux@41004400 {
97			compatible = "atmel,sam0-pinmux";
98			reg = <0x41004400 0x80>;
99		};
100
101		pinmux_b: pinmux@41004480 {
102			compatible = "atmel,sam0-pinmux";
103			reg = <0x41004480 0x80>;
104		};
105
106		wdog: watchdog@40001000 {
107			compatible = "atmel,sam0-watchdog";
108			reg = <0x40001000 9>;
109			interrupts = <2 0>;
110		};
111
112		sercom0: sercom@42000800 {
113			compatible = "atmel,sam0-sercom";
114			reg = <0x42000800 0x40>;
115			status = "disabled";
116		};
117
118		sercom1: sercom@42000c00 {
119			compatible = "atmel,sam0-sercom";
120			reg = <0x42000c00 0x40>;
121			status = "disabled";
122		};
123
124		sercom2: sercom@42001000 {
125			compatible = "atmel,sam0-sercom";
126			reg = <0x42001000 0x40>;
127			status = "disabled";
128		};
129
130		sercom3: sercom@42001400 {
131			compatible = "atmel,sam0-sercom";
132			reg = <0x42001400 0x40>;
133			status = "disabled";
134		};
135
136		sercom4: sercom@42001800 {
137			compatible = "atmel,sam0-sercom";
138			reg = <0x42001800 0x40>;
139			status = "disabled";
140		};
141
142		sercom5: sercom@42001c00 {
143			compatible = "atmel,sam0-sercom";
144			reg = <0x42001c00 0x40>;
145			status = "disabled";
146		};
147
148		tc4: tc@42003000 {
149			compatible = "atmel,sam0-tc32";
150			reg = <0x42003000 0x20>;
151		};
152
153		pinctrl: pinctrl@41004400 {
154			compatible = "atmel,sam0-pinctrl";
155			#address-cells = <1>;
156			#size-cells = <1>;
157			ranges = <0x41004400 0x41004400 0x100>;
158
159			porta: gpio@41004400 {
160				compatible = "atmel,sam0-gpio";
161				reg = <0x41004400 0x80>;
162				gpio-controller;
163				#gpio-cells = <2>;
164				#atmel,pin-cells = <2>;
165
166			};
167
168			portb: gpio@41004480 {
169				compatible = "atmel,sam0-gpio";
170				reg = <0x41004480 0x80>;
171				gpio-controller;
172				#gpio-cells = <2>;
173				#atmel,pin-cells = <2>;
174			};
175		};
176
177		rtc: rtc@40001400 {
178			compatible = "atmel,sam0-rtc";
179			reg = <0x40001400 0x1C>;
180			interrupts = <3 0>;
181			clock-generator = <0>;
182			status = "disabled";
183		};
184
185		adc: adc@42004000 {
186			compatible = "atmel,sam0-adc";
187			reg = <0x42004000 0x2B>;
188
189			/*
190			 * 2.1 MHz max, so clock it with the
191			 * 8 MHz GCLK / 4 = 2 MHz
192			 */
193			gclk = <3>;
194			prescaler = <4>;
195			#io-channel-cells = <1>;
196		};
197
198		dac0: dac@42004800 {
199			compatible = "atmel,sam0-dac";
200			status = "disabled";
201			reg = <0x42004800 0x10>;
202			#io-channel-cells = <0>;
203		};
204	};
205};
206
207&nvic {
208	arm,num-irq-priority-bits = <2>;
209};
210