1/*
2 * Copyright (c) 2017 Google LLC.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <arm/armv6-m.dtsi>
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/i2c/i2c.h>
11
12#include "samd2x-pinctrl.dtsi"
13
14/ {
15	aliases {
16		watchdog0 = &wdog;
17	};
18
19	chosen {
20		zephyr,flash-controller = &nvmctrl;
21	};
22
23	cpus {
24		#address-cells = <1>;
25		#size-cells = <0>;
26
27		cpu0: cpu@0 {
28			device_type = "cpu";
29			compatible = "arm,cortex-m0+";
30			reg = <0>;
31		};
32	};
33
34	sram0: memory@20000000 {
35		compatible = "mmio-sram";
36		reg = <0x20000000 0x8000>;
37	};
38
39	id: device_id@80a00c {
40		compatible = "atmel,sam0-id";
41		reg =	<0x0080A00C 0x4>,
42			<0x0080A040 0x4>,
43			<0x0080A044 0x4>,
44			<0x0080A048 0x4>;
45	};
46
47	aliases {
48		port-a = &porta;
49		port-b = &portb;
50		adc-0 = &adc;
51
52		sercom-0 = &sercom0;
53		sercom-1 = &sercom1;
54		sercom-2 = &sercom2;
55		sercom-3 = &sercom3;
56		sercom-4 = &sercom4;
57		sercom-5 = &sercom5;
58
59		tc-4 = &tc4;
60	};
61
62	soc {
63		nvmctrl: nvmctrl@41004000  {
64			compatible = "atmel,sam0-nvmctrl";
65			label = "FLASH_CTRL";
66			reg = <0x41004000 0x22>;
67			interrupts = <5 0>;
68			lock-regions = <16>;
69
70			#address-cells = <1>;
71			#size-cells = <1>;
72
73			flash0: flash@0 {
74				compatible = "soc-nv-flash";
75				label = "FLASH_0";
76				reg = <0 0x40000>;
77				write-block-size = <4>;
78			};
79		};
80
81		pm: pm@40000400 {
82			compatible = "atmel,samd2x-pm";
83			reg = <0x40000400 0x400>;
84			interrupts = <0 0>;
85			#clock-cells = <2>;
86		};
87
88		gclk: gclk@40000c00 {
89			compatible = "atmel,samd2x-gclk";
90			reg = <0x40000c00 0x400>;
91			#clock-cells = <1>;
92		};
93
94		eic: eic@40001800 {
95			compatible = "atmel,sam0-eic";
96			reg = <0x40001800 0x1C>;
97			interrupts = <4 0>;
98			label = "EIC";
99		};
100
101		pinmux_a: pinmux@41004400 {
102			compatible = "atmel,sam0-pinmux";
103			reg = <0x41004400 0x80>;
104		};
105
106		pinmux_b: pinmux@41004480 {
107			compatible = "atmel,sam0-pinmux";
108			reg = <0x41004480 0x80>;
109		};
110
111		wdog: watchdog@40001000 {
112			compatible = "atmel,sam0-watchdog";
113			reg = <0x40001000 9>;
114			interrupts = <2 0>;
115			label = "WATCHDOG_0";
116		};
117
118		sercom0: sercom@42000800 {
119			compatible = "atmel,sam0-sercom";
120			reg = <0x42000800 0x40>;
121			status = "disabled";
122			label = "SERCOM0";
123		};
124
125		sercom1: sercom@42000c00 {
126			compatible = "atmel,sam0-sercom";
127			reg = <0x42000c00 0x40>;
128			status = "disabled";
129			label = "SERCOM1";
130		};
131
132		sercom2: sercom@42001000 {
133			compatible = "atmel,sam0-sercom";
134			reg = <0x42001000 0x40>;
135			status = "disabled";
136			label = "SERCOM2";
137		};
138
139		sercom3: sercom@42001400 {
140			compatible = "atmel,sam0-sercom";
141			reg = <0x42001400 0x40>;
142			status = "disabled";
143			label = "SERCOM3";
144		};
145
146		sercom4: sercom@42001800 {
147			compatible = "atmel,sam0-sercom";
148			reg = <0x42001800 0x40>;
149			status = "disabled";
150			label = "SERCOM4";
151		};
152
153		sercom5: sercom@42001c00 {
154			compatible = "atmel,sam0-sercom";
155			reg = <0x42001c00 0x40>;
156			status = "disabled";
157			label = "SERCOM5";
158		};
159
160		tc4: tc@42003000 {
161			compatible = "atmel,sam0-tc32";
162			reg = <0x42003000 0x20>;
163			label = "TIMER_4";
164		};
165
166		pinctrl@41004400 {
167			compatible = "atmel,sam0-pinctrl";
168			#address-cells = <1>;
169			#size-cells = <1>;
170			ranges = <0x41004400 0x41004400 0x100>;
171
172			porta: gpio@41004400 {
173				compatible = "atmel,sam0-gpio";
174				reg = <0x41004400 0x80>;
175				label = "PORTA";
176				gpio-controller;
177				#gpio-cells = <2>;
178				#atmel,pin-cells = <2>;
179
180			};
181
182			portb: gpio@41004480 {
183				compatible = "atmel,sam0-gpio";
184				reg = <0x41004480 0x80>;
185				label = "PORTB";
186				gpio-controller;
187				#gpio-cells = <2>;
188				#atmel,pin-cells = <2>;
189			};
190		};
191
192		rtc: rtc@40001400 {
193			compatible = "atmel,sam0-rtc";
194			reg = <0x40001400 0x1C>;
195			interrupts = <3 0>;
196			clock-generator = <0>;
197			status = "disabled";
198			label = "RTC";
199		};
200
201		adc: adc@42004000 {
202			compatible = "atmel,sam0-adc";
203			reg = <0x42004000 0x2B>;
204			label = "ADC_0";
205
206			/*
207			 * 2.1 MHz max, so clock it with the
208			 * 8 MHz GCLK / 4 = 2 MHz
209			 */
210			gclk = <3>;
211			prescaler = <4>;
212			#io-channel-cells = <1>;
213		};
214
215		dac0: dac@42004800 {
216			compatible = "atmel,sam0-dac";
217			status = "disabled";
218			reg = <0x42004800 0x10>;
219			label = "DAC_0";
220			#io-channel-cells = <0>;
221		};
222	};
223};
224
225&nvic {
226	arm,num-irq-priority-bits = <2>;
227};
228