1/*
2 * Copyright (c) 2022 Kamil Serwus
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <arm/armv6-m.dtsi>
9#include <zephyr/dt-bindings/adc/adc.h>
10#include <zephyr/dt-bindings/gpio/gpio.h>
11#include <zephyr/dt-bindings/i2c/i2c.h>
12#include <zephyr/dt-bindings/pwm/pwm.h>
13
14/ {
15	aliases {
16		adc-0 = &adc0;
17
18		port-a = &porta;
19		port-b = &portb;
20		port-c = &portc;
21
22		sercom-0 = &sercom0;
23		sercom-1 = &sercom1;
24		sercom-2 = &sercom2;
25		sercom-3 = &sercom3;
26
27		tcc-0 = &tcc0;
28		tcc-1 = &tcc1;
29		tcc-2 = &tcc2;
30
31		watchdog0 = &wdog;
32	};
33
34	chosen {
35		zephyr,flash-controller = &nvmctrl;
36	};
37
38	cpus {
39		#address-cells = <1>;
40		#size-cells = <0>;
41
42		cpu0: cpu@0 {
43			compatible = "arm,cortex-m0+";
44			reg = <0>;
45
46			device_type = "cpu";
47		};
48	};
49
50	sram0: memory@20000000 {
51		compatible = "mmio-sram";
52	};
53
54	id: device_id@80a00c {
55		compatible = "atmel,sam0-id";
56		reg =	<0x0080A00C 0x4>,
57			<0x0080A040 0x4>,
58			<0x0080A044 0x4>,
59			<0x0080A048 0x4>;
60	};
61
62	soc {
63		nvmctrl: nvmctrl@41004000  {
64			compatible = "atmel,sam0-nvmctrl";
65			reg = <0x41004000 0x22>;
66			interrupts = <6 0>;
67
68			#address-cells = <1>;
69			#size-cells = <1>;
70
71			lock-regions = <16>;
72
73			flash0: flash@0 {
74				compatible = "soc-nv-flash";
75
76				write-block-size = <4>;
77			};
78		};
79
80		mclk: mclk@40000800 {
81			compatible = "atmel,samc2x-mclk";
82			reg = <0x40000800 0x400>;
83
84			#clock-cells = <2>;
85		};
86
87		gclk: gclk@40001c00 {
88			compatible = "atmel,samc2x-gclk";
89			reg = <0x40001c00 0x400>;
90
91			#clock-cells = <1>;
92		};
93
94		eic: eic@40002800 {
95			compatible = "atmel,sam0-eic";
96			reg = <0x40002800 0x1C>;
97			interrupts = <3 0>;
98		};
99
100		pinmux_a: pinmux@41000000 {
101			compatible = "atmel,sam0-pinmux";
102			reg = <0x41000000 0x80>;
103		};
104
105		wdog: watchdog@40002000 {
106			compatible = "atmel,sam0-watchdog";
107			reg = <0x40002000 9>;
108			interrupts = <1 0>;
109		};
110
111		dmac: dmac@41006000 {
112			compatible = "atmel,sam0-dmac";
113			reg = <0x41006000 0x50>;
114			interrupts = <7 0>;
115			status = "disabled";
116
117			#dma-cells = <2>;
118		};
119
120		adc0: adc@42004400 {
121			compatible = "atmel,sam0-adc";
122			reg = <0x42004400 0x30>;
123			interrupts = <25 0>;
124			interrupt-names = "resrdy";
125			clocks = <&gclk 33>, <&mclk 0x1c 17>;
126			clock-names = "GCLK", "MCLK";
127			status = "disabled";
128
129			#io-channel-cells = <1>;
130
131			gclk = <0>;
132			prescaler = <4>;
133		};
134
135		sercom0: sercom@42000400 {
136			compatible = "atmel,sam0-sercom";
137			reg = <0x42000400 0x40>;
138			interrupts = <9 0>;
139			clocks = <&gclk 19>, <&mclk 0x1c 1>;
140			clock-names = "GCLK", "MCLK";
141			status = "disabled";
142		};
143
144		sercom1: sercom@42000800 {
145			compatible = "atmel,sam0-sercom";
146			reg = <0x42000800 0x40>;
147			interrupts = <10 0>;
148			clocks = <&gclk 20>, <&mclk 0x1c 2>;
149			clock-names = "GCLK", "MCLK";
150			status = "disabled";
151		};
152
153		sercom2: sercom@42000c00 {
154			compatible = "atmel,sam0-sercom";
155			reg = <0x42000c00 0x40>;
156			interrupts = <11 0>;
157			clocks = <&gclk 21>, <&mclk 0x1c 3>;
158			clock-names = "GCLK", "MCLK";
159			status = "disabled";
160		};
161
162		sercom3: sercom@42001000 {
163			compatible = "atmel,sam0-sercom";
164			reg = <0x42001000 0x40>;
165			interrupts = <12 0>;
166			clocks = <&gclk 22>, <&mclk 0x1c 4>;
167			clock-names = "GCLK", "MCLK";
168			status = "disabled";
169		};
170
171		tcc0: tcc@42002400 {
172			compatible = "atmel,sam0-tcc";
173			reg = <0x42002400 0x80>;
174			interrupts = <17 0>;
175			clocks = <&gclk 28>, <&mclk 0x1c 9>;
176			clock-names = "GCLK", "MCLK";
177			status = "disabled";
178
179			channels = <4>;
180			counter-size = <24>;
181		};
182
183		tcc1: tcc@42002800 {
184			compatible = "atmel,sam0-tcc";
185			reg = <0x42002800 0x80>;
186			interrupts = <18 0>;
187			clocks = <&gclk 28>, <&mclk 0x1c 10>;
188			clock-names = "GCLK", "MCLK";
189			status = "disabled";
190
191			channels = <4>;
192			counter-size = <24>;
193		};
194
195		tcc2: tcc@42002c00 {
196			compatible = "atmel,sam0-tcc";
197			reg = <0x42002c00 0x80>;
198			interrupts = <19 0>;
199			clocks = <&gclk 29>, <&mclk 0x1c 11>;
200			clock-names = "GCLK", "MCLK";
201			status = "disabled";
202
203			channels = <2>;
204			counter-size = <16>;
205		};
206
207		pinctrl: pinctrl@41000000 {
208			compatible = "atmel,sam0-pinctrl";
209			ranges = <0x41000000 0x41000000 0x180>;
210
211			#address-cells = <1>;
212			#size-cells = <1>;
213
214			porta: gpio@41000000 {
215				compatible = "atmel,sam0-gpio";
216				reg = <0x41000000 0x80>;
217
218				#atmel,pin-cells = <2>;
219				#gpio-cells = <2>;
220
221				gpio-controller;
222			};
223
224			portb: gpio@41000080 {
225				compatible = "atmel,sam0-gpio";
226				reg = <0x41000080 0x80>;
227
228				#atmel,pin-cells = <2>;
229				#gpio-cells = <2>;
230
231				gpio-controller;
232			};
233
234			portc: gpio@41000100 {
235				compatible = "atmel,sam0-gpio";
236				reg = <0x41000100 0x80>;
237
238				#atmel,pin-cells = <2>;
239				#gpio-cells = <2>;
240
241				gpio-controller;
242			};
243		};
244
245		rtc: rtc@40002400 {
246			compatible = "atmel,sam0-rtc";
247			reg = <0x40002400 0x1C>;
248			interrupts = <3 0>;
249			status = "disabled";
250
251			clock-generator = <0>;
252		};
253	};
254};
255
256&nvic {
257	arm,num-irq-priority-bits = <2>;
258};
259