1/* 2 * Copyright (c) 2017 Justin Watson 3 * Copyright (c) 2019 Gerson Fernando Budke 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 */ 7 8#include <arm/armv7-m.dtsi> 9#include <zephyr/dt-bindings/adc/adc.h> 10#include <zephyr/dt-bindings/i2c/i2c.h> 11#include <zephyr/dt-bindings/gpio/gpio.h> 12#include <zephyr/dt-bindings/pwm/pwm.h> 13#include <zephyr/dt-bindings/clock/atmel_sam_pmc.h> 14 15/ { 16 aliases { 17 watchdog0 = &wdt; 18 }; 19 20 chosen { 21 zephyr,flash-controller = &eefc; 22 }; 23 24 cpus { 25 #address-cells = <1>; 26 #size-cells = <0>; 27 28 cpu0: cpu@0 { 29 device_type = "cpu"; 30 compatible = "arm,cortex-m4"; 31 reg = <0>; 32 #address-cells = <1>; 33 #size-cells = <1>; 34 35 mpu: mpu@e000ed90 { 36 compatible = "arm,armv7m-mpu"; 37 reg = <0xe000ed90 0x40>; 38 }; 39 }; 40 }; 41 42 soc { 43 pmc: pmc@400e0400 { 44 compatible = "atmel,sam-pmc"; 45 reg = <0x400e0400 0x200>; 46 interrupts = <5 0>; 47 #clock-cells = <2>; 48 status = "okay"; 49 }; 50 51 supc: supc@400e1410 { 52 compatible = "atmel,sam-supc"; 53 reg = <0x400e1410 0x20>; 54 #wakeup-source-id-cells = <1>; 55 status = "okay"; 56 }; 57 58 sram0: memory@20100000 { 59 compatible = "mmio-sram"; 60 }; 61 62 eefc: flash-controller@400e0a00 { 63 compatible = "atmel,sam-flash-controller"; 64 reg = <0x400e0a00 0x200>; 65 interrupts = <6 0>; 66 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 67 68 #address-cells = <1>; 69 #size-cells = <1>; 70 #erase-block-cells = <2>; 71 72 flash0: flash@400000 { 73 compatible = "atmel,sam-flash", "soc-nv-flash"; 74 write-block-size = <8>; 75 erase-block-size = <4096>; 76 }; 77 }; 78 79 wdt: watchdog@400e1450 { 80 compatible = "atmel,sam-watchdog"; 81 reg = <0x400e1450 0xc>; 82 interrupts = <4 0>; 83 clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; 84 status = "disabled"; 85 }; 86 87 twi0: i2c@40018000 { 88 compatible = "atmel,sam-i2c-twi"; 89 clock-frequency = <I2C_BITRATE_STANDARD>; 90 reg = <0x40018000 0x128>; 91 interrupts = <19 0>; 92 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 93 status = "disabled"; 94 #address-cells = <1>; 95 #size-cells = <0>; 96 }; 97 98 twi1: i2c@4001c000 { 99 compatible = "atmel,sam-i2c-twi"; 100 clock-frequency = <I2C_BITRATE_STANDARD>; 101 reg = <0x4001c000 0x128>; 102 interrupts = <20 0>; 103 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 104 status = "disabled"; 105 #address-cells = <1>; 106 #size-cells = <0>; 107 }; 108 109 spi0: spi@40008000 { 110 compatible = "atmel,sam-spi"; 111 #address-cells = <1>; 112 #size-cells = <0>; 113 reg = <0x40008000 0x4000>; 114 interrupts = <21 0>; 115 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 116 status = "disabled"; 117 }; 118 119 uart0: uart@400e0600 { 120 compatible = "atmel,sam-uart"; 121 reg = <0x400e0600 0x200>; 122 interrupts = <8 1>; 123 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; 124 status = "disabled"; 125 }; 126 127 uart1: uart@400e0800 { 128 compatible = "atmel,sam-uart"; 129 reg = <0x400e0800 0x200>; 130 interrupts = <9 1>; 131 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; 132 status = "disabled"; 133 }; 134 135 pwm0: pwm@40020000 { 136 compatible = "atmel,sam-pwm"; 137 reg = <0x40020000 0x4000>; 138 interrupts = <31 1>; 139 clocks = <&pmc PMC_TYPE_PERIPHERAL 31>; 140 prescaler = <10>; 141 divider = <1>; 142 #pwm-cells = <3>; 143 status = "disabled"; 144 }; 145 146 usart0: usart@40024000 { 147 compatible = "atmel,sam-usart"; 148 reg = <0x40024000 0x130>; 149 interrupts = <14 1>; 150 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; 151 status = "disabled"; 152 }; 153 154 usart1: usart@40028000 { 155 compatible = "atmel,sam-usart"; 156 reg = <0x40028000 0x130>; 157 interrupts = <15 1>; 158 clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; 159 status = "disabled"; 160 }; 161 162 pinctrl: pinctrl@400e0e00 { 163 compatible = "atmel,sam-pinctrl"; 164 #address-cells = <1>; 165 #size-cells = <1>; 166 ranges = <0x400e0e00 0x400e0e00 0x600>; 167 status = "okay"; 168 169 pioa: gpio@400e0e00 { 170 compatible = "atmel,sam-gpio"; 171 reg = <0x400e0e00 0x190>; 172 interrupts = <11 1>; 173 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 174 gpio-controller; 175 #gpio-cells = <2>; 176 #atmel,pin-cells = <2>; 177 }; 178 179 piob: gpio@400e1000 { 180 compatible = "atmel,sam-gpio"; 181 reg = <0x400e1000 0x190>; 182 interrupts = <12 1>; 183 clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; 184 gpio-controller; 185 #gpio-cells = <2>; 186 #atmel,pin-cells = <2>; 187 }; 188 189 pioc: gpio@400e1200 { 190 compatible = "atmel,sam-gpio"; 191 reg = <0x400e1200 0x190>; 192 interrupts = <13 1>; 193 clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; 194 gpio-controller; 195 #gpio-cells = <2>; 196 #atmel,pin-cells = <2>; 197 }; 198 }; 199 200 tc0: tc@40010000 { 201 compatible = "atmel,sam-tc"; 202 reg = <0x40010000 0x100>; 203 interrupts = <23 0 204 24 0 205 25 0>; 206 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, 207 <&pmc PMC_TYPE_PERIPHERAL 24>, 208 <&pmc PMC_TYPE_PERIPHERAL 25>; 209 status = "disabled"; 210 }; 211 212 tc1: tc@40014000 { 213 compatible = "atmel,sam-tc"; 214 reg = <0x40014000 0x100>; 215 interrupts = <26 0 216 27 0 217 28 0>; 218 clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, 219 <&pmc PMC_TYPE_PERIPHERAL 27>, 220 <&pmc PMC_TYPE_PERIPHERAL 28>; 221 status = "disabled"; 222 }; 223 224 adc0: adc@40038000 { 225 compatible = "atmel,sam-adc"; 226 reg = <0x40038000 0x4000>; 227 interrupts = <29 1>; 228 clocks = <&pmc PMC_TYPE_PERIPHERAL 29>; 229 #address-cells = <1>; 230 #size-cells = <0>; 231 #io-channel-cells = <1>; 232 status = "disabled"; 233 }; 234 235 rstc: rstc@400e1400 { 236 compatible = "atmel,sam-rstc"; 237 reg = <0x400e1400 0x10>; 238 clocks = <&pmc PMC_TYPE_PERIPHERAL 1>; 239 user-nrst; 240 }; 241 242 smc: smc@400e0000 { 243 compatible = "atmel,sam-smc"; 244 #address-cells = <1>; 245 #size-cells = <0>; 246 reg = <0x400e0000 0x200>; 247 clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; 248 status = "disabled"; 249 }; 250 251 rtc: rtc@400e1460 { 252 compatible = "atmel,sam-rtc"; 253 reg = <0x400e1460 0x100>; 254 interrupts = <2 0>; 255 clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; 256 alarms-count = <1>; 257 status = "disabled"; 258 }; 259 }; 260}; 261 262&nvic { 263 arm,num-irq-priority-bits = <4>; 264}; 265
