1 /*
2 * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Licensed under the Apache License, Version 2.0 (the License); you may
7 * not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19 /* ----------------------------------------------------------------------
20 * Project: CMSIS NN Library
21 * Title: arm_q7_to_q15_reordered_no_shift.c
22 * Description: Converts the elements of the Q7 vector to reordered Q15 vector without left-shift
23 *
24 * $Date: May 29, 2020
25 * $Revision: V.1.0.1
26 *
27 * Target Processor: Cortex-M cores
28 *
29 * -------------------------------------------------------------------- */
30
31 #include "arm_nnsupportfunctions.h"
32
33 /**
34 * @ingroup groupSupport
35 */
36
37 /**
38 * @addtogroup nndata_convert
39 * @{
40 */
41
42 /**
43 * @brief Converts the elements of the Q7 vector to reordered Q15 vector without left-shift
44 * @param[in] *pSrc points to the Q7 input vector
45 * @param[out] *pDst points to the Q15 output vector
46 * @param[in] blockSize length of the input vector
47 *
48 * @details
49 *
50 * This function does the q7 to q15 expansion with re-ordering
51 *
52 * <pre>
53 * | A1 | A2 | A3 | A4 |
54 *
55 * 0 7 8 15 16 23 24 31
56 * </pre>
57 *
58 * is converted into:
59 *
60 * <pre>
61 * | A1 | A3 | and | A2 | A4 |
62 *
63 * 0 15 16 31 0 15 16 31
64 * </pre>
65 *
66 *
67 * This looks strange but is natural considering how sign-extension is done at
68 * assembly level.
69 *
70 * The expansion of other other oprand will follow the same rule so that the end
71 * results are the same.
72 *
73 * The tail (i.e., last (N % 4) elements) will still be in original order.
74 *
75 */
76
arm_q7_to_q15_reordered_no_shift(const q7_t * pSrc,q15_t * pDst,uint32_t blockSize)77 void arm_q7_to_q15_reordered_no_shift(const q7_t *pSrc, q15_t *pDst, uint32_t blockSize)
78 {
79 const q7_t *pIn = pSrc; /* Src pointer */
80 uint32_t blkCnt; /* loop counter */
81
82 #ifndef ARM_MATH_CM0_FAMILY
83 q31_t in;
84 q31_t in1, in2;
85
86 /* Run the below code for Cortex-M4 and Cortex-M3 */
87
88 /*loop Unrolling */
89 blkCnt = blockSize >> 2u;
90
91 /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
92 ** a second loop below computes the remaining 1 to 3 samples. */
93 while (blkCnt > 0u)
94 {
95 /* C = (q15_t) A << 8 */
96 /* convert from q7 to q15 and then store the results in the destination buffer */
97 in = arm_nn_read_q7x4_ia(&pIn);
98
99 /* rotatate in by 8 and extend two q7_t values to q15_t values */
100 in1 = __SXTB16(__ROR((uint32_t)in, 8));
101
102 /* extend remainig two q7_t values to q15_t values */
103 in2 = __SXTB16(in);
104
105 #ifndef ARM_MATH_BIG_ENDIAN
106 *__SIMD32(pDst)++ = in2;
107 *__SIMD32(pDst)++ = in1;
108 #else
109 *__SIMD32(pDst)++ = in1;
110 *__SIMD32(pDst)++ = in2;
111 #endif
112
113 /* Decrement the loop counter */
114 blkCnt--;
115 }
116
117 /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
118 ** No loop unrolling is used. */
119 blkCnt = blockSize % 0x4u;
120
121 #else
122
123 /* Run the below code for Cortex-M0 */
124
125 /* Loop over blockSize number of values */
126 blkCnt = blockSize;
127
128 #endif /* #ifndef ARM_MATH_CM0_FAMILY */
129
130 while (blkCnt > 0u)
131 {
132 /* C = (q15_t) A << 8 */
133 /* convert from q7 to q15 and then store the results in the destination buffer */
134 *pDst++ = (q15_t)*pIn++;
135
136 /* Decrement the loop counter */
137 blkCnt--;
138 }
139 }
140
141 /**
142 * @} end of q7_to_x group
143 */
144
