1 /*
2 * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <platform_def.h>
10
11 #include <arch.h>
12 #include <bl1/bl1.h>
13 #include <common/bl_common.h>
14 #include <lib/fconf/fconf.h>
15 #include <lib/fconf/fconf_dyn_cfg_getter.h>
16 #include <lib/utils.h>
17 #include <lib/xlat_tables/xlat_tables_compat.h>
18 #include <plat/arm/common/plat_arm.h>
19 #include <plat/common/platform.h>
20
21 /* Weak definitions may be overridden in specific ARM standard platform */
22 #pragma weak bl1_early_platform_setup
23 #pragma weak bl1_plat_arch_setup
24 #pragma weak bl1_plat_sec_mem_layout
25 #pragma weak arm_bl1_early_platform_setup
26 #pragma weak bl1_plat_prepare_exit
27 #pragma weak bl1_plat_get_next_image_id
28 #pragma weak plat_arm_bl1_fwu_needed
29 #pragma weak arm_bl1_plat_arch_setup
30 #pragma weak arm_bl1_platform_setup
31
32 #define MAP_BL1_TOTAL MAP_REGION_FLAT( \
33 bl1_tzram_layout.total_base, \
34 bl1_tzram_layout.total_size, \
35 MT_MEMORY | MT_RW | EL3_PAS)
36 /*
37 * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section
38 * otherwise one region is defined containing both
39 */
40 #if SEPARATE_CODE_AND_RODATA
41 #define MAP_BL1_RO MAP_REGION_FLAT( \
42 BL_CODE_BASE, \
43 BL1_CODE_END - BL_CODE_BASE, \
44 MT_CODE | EL3_PAS), \
45 MAP_REGION_FLAT( \
46 BL1_RO_DATA_BASE, \
47 BL1_RO_DATA_END \
48 - BL_RO_DATA_BASE, \
49 MT_RO_DATA | EL3_PAS)
50 #else
51 #define MAP_BL1_RO MAP_REGION_FLAT( \
52 BL_CODE_BASE, \
53 BL1_CODE_END - BL_CODE_BASE, \
54 MT_CODE | EL3_PAS)
55 #endif
56
57 /* Data structure which holds the extents of the trusted SRAM for BL1*/
58 static meminfo_t bl1_tzram_layout;
59
60 /* Boolean variable to hold condition whether firmware update needed or not */
61 static bool is_fwu_needed;
62
bl1_plat_sec_mem_layout(void)63 struct meminfo *bl1_plat_sec_mem_layout(void)
64 {
65 return &bl1_tzram_layout;
66 }
67
68 /*******************************************************************************
69 * BL1 specific platform actions shared between ARM standard platforms.
70 ******************************************************************************/
arm_bl1_early_platform_setup(void)71 void arm_bl1_early_platform_setup(void)
72 {
73
74 #if !ARM_DISABLE_TRUSTED_WDOG
75 /* Enable watchdog */
76 plat_arm_secure_wdt_start();
77 #endif
78
79 /* Initialize the console to provide early debug support */
80 arm_console_boot_init();
81
82 /* Allow BL1 to see the whole Trusted RAM */
83 bl1_tzram_layout.total_base = ARM_BL_RAM_BASE;
84 bl1_tzram_layout.total_size = ARM_BL_RAM_SIZE;
85 }
86
bl1_early_platform_setup(void)87 void bl1_early_platform_setup(void)
88 {
89 arm_bl1_early_platform_setup();
90
91 /*
92 * Initialize Interconnect for this cluster during cold boot.
93 * No need for locks as no other CPU is active.
94 */
95 plat_arm_interconnect_init();
96 /*
97 * Enable Interconnect coherency for the primary CPU's cluster.
98 */
99 plat_arm_interconnect_enter_coherency();
100 }
101
102 /******************************************************************************
103 * Perform the very early platform specific architecture setup shared between
104 * ARM standard platforms. This only does basic initialization. Later
105 * architectural setup (bl1_arch_setup()) does not do anything platform
106 * specific.
107 *****************************************************************************/
arm_bl1_plat_arch_setup(void)108 void arm_bl1_plat_arch_setup(void)
109 {
110 #if USE_COHERENT_MEM && !ARM_CRYPTOCELL_INTEG
111 /*
112 * Ensure ARM platforms don't use coherent memory in BL1 unless
113 * cryptocell integration is enabled.
114 */
115 assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U);
116 #endif
117
118 const mmap_region_t bl_regions[] = {
119 MAP_BL1_TOTAL,
120 MAP_BL1_RO,
121 #if USE_ROMLIB
122 ARM_MAP_ROMLIB_CODE,
123 ARM_MAP_ROMLIB_DATA,
124 #endif
125 #if ARM_CRYPTOCELL_INTEG
126 ARM_MAP_BL_COHERENT_RAM,
127 #endif
128 {0}
129 };
130
131 setup_page_tables(bl_regions, plat_arm_get_mmap());
132 #ifdef __aarch64__
133 enable_mmu_el3(0);
134 #else
135 enable_mmu_svc_mon(0);
136 #endif /* __aarch64__ */
137
138 arm_setup_romlib();
139 }
140
bl1_plat_arch_setup(void)141 void bl1_plat_arch_setup(void)
142 {
143 arm_bl1_plat_arch_setup();
144 }
145
146 /*
147 * Perform the platform specific architecture setup shared between
148 * ARM standard platforms.
149 */
arm_bl1_platform_setup(void)150 void arm_bl1_platform_setup(void)
151 {
152 const struct dyn_cfg_dtb_info_t *fw_config_info;
153 image_desc_t *desc;
154 uint32_t fw_config_max_size;
155 int err = -1;
156
157 /* Initialise the IO layer and register platform IO devices */
158 plat_arm_io_setup();
159
160 /* Check if we need FWU before further processing */
161 is_fwu_needed = plat_arm_bl1_fwu_needed();
162 if (is_fwu_needed) {
163 ERROR("Skip platform setup as FWU detected\n");
164 return;
165 }
166
167 /* Set global DTB info for fixed fw_config information */
168 fw_config_max_size = ARM_FW_CONFIG_LIMIT - ARM_FW_CONFIG_BASE;
169 set_config_info(ARM_FW_CONFIG_BASE, ~0UL, fw_config_max_size, FW_CONFIG_ID);
170
171 /* Fill the device tree information struct with the info from the config dtb */
172 err = fconf_load_config(FW_CONFIG_ID);
173 if (err < 0) {
174 ERROR("Loading of FW_CONFIG failed %d\n", err);
175 plat_error_handler(err);
176 }
177
178 /*
179 * FW_CONFIG loaded successfully. If FW_CONFIG device tree parsing
180 * is successful then load TB_FW_CONFIG device tree.
181 */
182 fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, FW_CONFIG_ID);
183 if (fw_config_info != NULL) {
184 err = fconf_populate_dtb_registry(fw_config_info->config_addr);
185 if (err < 0) {
186 ERROR("Parsing of FW_CONFIG failed %d\n", err);
187 plat_error_handler(err);
188 }
189 /* load TB_FW_CONFIG */
190 err = fconf_load_config(TB_FW_CONFIG_ID);
191 if (err < 0) {
192 ERROR("Loading of TB_FW_CONFIG failed %d\n", err);
193 plat_error_handler(err);
194 }
195 } else {
196 ERROR("Invalid FW_CONFIG address\n");
197 plat_error_handler(err);
198 }
199
200 /* The BL2 ep_info arg0 is modified to point to FW_CONFIG */
201 desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
202 assert(desc != NULL);
203 desc->ep_info.args.arg0 = fw_config_info->config_addr;
204
205 #if CRYPTO_SUPPORT
206 /* Share the Mbed TLS heap info with other images */
207 arm_bl1_set_mbedtls_heap();
208 #endif /* CRYPTO_SUPPORT */
209
210 /*
211 * Allow access to the System counter timer module and program
212 * counter frequency for non secure images during FWU
213 */
214 #ifdef ARM_SYS_TIMCTL_BASE
215 arm_configure_sys_timer();
216 #endif
217 #if (ARM_ARCH_MAJOR > 7) || defined(ARMV7_SUPPORTS_GENERIC_TIMER)
218 write_cntfrq_el0(plat_get_syscnt_freq2());
219 #endif
220 }
221
bl1_plat_prepare_exit(entry_point_info_t * ep_info)222 void bl1_plat_prepare_exit(entry_point_info_t *ep_info)
223 {
224 #if !ARM_DISABLE_TRUSTED_WDOG
225 /* Disable watchdog before leaving BL1 */
226 plat_arm_secure_wdt_stop();
227 #endif
228
229 #ifdef EL3_PAYLOAD_BASE
230 /*
231 * Program the EL3 payload's entry point address into the CPUs mailbox
232 * in order to release secondary CPUs from their holding pen and make
233 * them jump there.
234 */
235 plat_arm_program_trusted_mailbox(ep_info->pc);
236 dsbsy();
237 sev();
238 #endif
239 }
240
241 /*
242 * On Arm platforms, the FWU process is triggered when the FIP image has
243 * been tampered with.
244 */
plat_arm_bl1_fwu_needed(void)245 bool plat_arm_bl1_fwu_needed(void)
246 {
247 return !arm_io_is_toc_valid();
248 }
249
250 /*******************************************************************************
251 * The following function checks if Firmware update is needed,
252 * by checking if TOC in FIP image is valid or not.
253 ******************************************************************************/
bl1_plat_get_next_image_id(void)254 unsigned int bl1_plat_get_next_image_id(void)
255 {
256 return is_fwu_needed ? NS_BL1U_IMAGE_ID : BL2_IMAGE_ID;
257 }
258
