1 /* ----------------------------------------------------------------------
2 * Project: CMSIS DSP Library
3 * Title: arm_biquad_cascade_df1_init_q15.c
4 * Description: Q15 Biquad cascade DirectFormI(DF1) filter initialization function
5 *
6 * $Date: 23 April 2021
7 * $Revision: V1.9.0
8 *
9 * Target Processor: Cortex-M and Cortex-A cores
10 * -------------------------------------------------------------------- */
11 /*
12 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
13 *
14 * SPDX-License-Identifier: Apache-2.0
15 *
16 * Licensed under the Apache License, Version 2.0 (the License); you may
17 * not use this file except in compliance with the License.
18 * You may obtain a copy of the License at
19 *
20 * www.apache.org/licenses/LICENSE-2.0
21 *
22 * Unless required by applicable law or agreed to in writing, software
23 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
24 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
25 * See the License for the specific language governing permissions and
26 * limitations under the License.
27 */
28
29 #include "dsp/filtering_functions.h"
30
31 /**
32 @ingroup groupFilters
33 */
34
35 /**
36 @addtogroup BiquadCascadeDF1
37 @{
38 */
39
40 /**
41 @brief Initialization function for the Q15 Biquad cascade filter.
42 @param[in,out] S points to an instance of the Q15 Biquad cascade structure.
43 @param[in] numStages number of 2nd order stages in the filter.
44 @param[in] pCoeffs points to the filter coefficients.
45 @param[in] pState points to the state buffer.
46 @param[in] postShift Shift to be applied to the accumulator result. Varies according to the coefficients format
47
48 @par Coefficient and State Ordering
49 The coefficients are stored in the array <code>pCoeffs</code> in the following order:
50 <pre>
51 {b10, 0, b11, b12, a11, a12, b20, 0, b21, b22, a21, a22, ...}
52 </pre>
53 @par
54 where <code>b1x</code> and <code>a1x</code> are the coefficients for the first stage,
55 <code>b2x</code> and <code>a2x</code> are the coefficients for the second stage,
56 and so on. The <code>pCoeffs</code> array contains a total of <code>6*numStages</code> values.
57 The zero coefficient between <code>b1</code> and <code>b2</code> facilities use of 16-bit SIMD instructions on the Cortex-M4.
58 @par
59 The state variables are stored in the array <code>pState</code>.
60 Each Biquad stage has 4 state variables <code>x[n-1], x[n-2], y[n-1],</code> and <code>y[n-2]</code>.
61 The state variables are arranged in the <code>pState</code> array as:
62 <pre>
63 {x[n-1], x[n-2], y[n-1], y[n-2]}
64 </pre>
65 The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.
66 The state array has a total length of <code>4*numStages</code> values.
67 The state variables are updated after each block of data is processed; the coefficients are untouched.
68 */
69
arm_biquad_cascade_df1_init_q15(arm_biquad_casd_df1_inst_q15 * S,uint8_t numStages,const q15_t * pCoeffs,q15_t * pState,int8_t postShift)70 ARM_DSP_ATTRIBUTE void arm_biquad_cascade_df1_init_q15(
71 arm_biquad_casd_df1_inst_q15 * S,
72 uint8_t numStages,
73 const q15_t * pCoeffs,
74 q15_t * pState,
75 int8_t postShift)
76 {
77 /* Assign filter stages */
78 S->numStages = numStages;
79
80 /* Assign postShift to be applied to the output */
81 S->postShift = postShift;
82
83 /* Assign coefficient pointer */
84 S->pCoeffs = pCoeffs;
85
86 /* Clear state buffer and size is always 4 * numStages */
87 memset(pState, 0, (4U * (uint32_t) numStages) * sizeof(q15_t));
88
89 /* Assign state pointer */
90 S->pState = pState;
91 }
92
93 /**
94 @} end of BiquadCascadeDF1 group
95 */
96
