1 
2 /* ----------------------------------------------------------------------
3  * Project:      CMSIS DSP Library
4  * Title:        arm_biquad_cascade_df1_init_f16.c
5  * Description:  Floating-point Biquad cascade DirectFormI(DF1) filter initialization function
6  *
7  * $Date:        23 April 2021
8  * $Revision:    V1.9.0
9  *
10  * Target Processor: Cortex-M and Cortex-A cores
11  * -------------------------------------------------------------------- */
12 /*
13  * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
14  *
15  * SPDX-License-Identifier: Apache-2.0
16  *
17  * Licensed under the Apache License, Version 2.0 (the License); you may
18  * not use this file except in compliance with the License.
19  * You may obtain a copy of the License at
20  *
21  * www.apache.org/licenses/LICENSE-2.0
22  *
23  * Unless required by applicable law or agreed to in writing, software
24  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
25  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
26  * See the License for the specific language governing permissions and
27  * limitations under the License.
28  */
29 
30 #include "dsp/filtering_functions_f16.h"
31 
32 #if defined(ARM_FLOAT16_SUPPORTED)
33 /**
34   @ingroup groupFilters
35  */
36 
37 /**
38   @addtogroup BiquadCascadeDF1
39   @{
40  */
41 
42 /**
43   @brief         Initialization function for the floating-point Biquad cascade filter.
44   @param[in,out] S           points to an instance of the floating-point Biquad cascade structure.
45   @param[in]     numStages   number of 2nd order stages in the filter.
46   @param[in]     pCoeffs     points to the filter coefficients.
47   @param[in]     pState      points to the state buffer.
48 
49   @par           Coefficient and State Ordering
50                    The coefficients are stored in the array <code>pCoeffs</code> in the following order:
51   <pre>
52       {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
53   </pre>
54 
55   @par
56                    where <code>b1x</code> and <code>a1x</code> are the coefficients for the first stage,
57                    <code>b2x</code> and <code>a2x</code> are the coefficients for the second stage,
58                    and so on. The <code>pCoeffs</code> array contains a total of <code>5*numStages</code> values.
59   @par
60                    The <code>pState</code> is a pointer to state array.
61                    Each Biquad stage has 4 state variables <code>x[n-1], x[n-2], y[n-1],</code> and <code>y[n-2]</code>.
62                    The state variables are arranged in the <code>pState</code> array as:
63   <pre>
64       {x[n-1], x[n-2], y[n-1], y[n-2]}
65   </pre>
66                    The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.
67                    The state array has a total length of <code>4*numStages</code> values.
68                    The state variables are updated after each block of data is processed; the coefficients are untouched.
69 
70   @par             For MVE code, an additional buffer of modified coefficients is required.
71                    Its size is numStages and each element of this buffer has type arm_biquad_mod_coef_f16.
72                    So, its total size is 96*numStages float16_t elements.
73 
74                    The initialization function which must be used is arm_biquad_cascade_df1_mve_init_f16.
75  */
76 
77 
arm_biquad_cascade_df1_init_f16(arm_biquad_casd_df1_inst_f16 * S,uint8_t numStages,const float16_t * pCoeffs,float16_t * pState)78 ARM_DSP_ATTRIBUTE void arm_biquad_cascade_df1_init_f16(
79         arm_biquad_casd_df1_inst_f16 * S,
80         uint8_t numStages,
81   const float16_t * pCoeffs,
82         float16_t * pState)
83 {
84   /* Assign filter stages */
85   S->numStages = numStages;
86 
87   /* Assign coefficient pointer */
88   S->pCoeffs = pCoeffs;
89 
90   /* Clear state buffer and size is always 4 * numStages */
91   memset(pState, 0, (4U * (uint32_t) numStages) * sizeof(float16_t));
92 
93   /* Assign state pointer */
94   S->pState = pState;
95 }
96 
97 #if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE)
98 
99 /*
100 
101 The computation of the coefficients is done in float32 otherwise the
102 resulting filter is too different from the expected one.
103 
104 */
generateCoefsFastBiquadF16(float16_t b0,float16_t b1,float16_t b2,float16_t a1,float16_t a2,arm_biquad_mod_coef_f16 * newCoef)105 static void generateCoefsFastBiquadF16(float16_t b0, float16_t b1, float16_t b2, float16_t a1, float16_t a2,
106                                 arm_biquad_mod_coef_f16 * newCoef)
107 {
108     float32_t coeffs[8][12] = {
109         {0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, (float32_t)b0, (float32_t)b1, (float32_t)b2, (float32_t)a1, (float32_t)a2},
110         {0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, (float32_t)b0, (float32_t)b1, (float32_t)b2, 0.0f, (float32_t)a2, 0.0f},
111         {0.0f, 0.0f, 0.0f, 0.0f, 0.0f, (float32_t)b0, (float32_t)b1, (float32_t)b2, 0.0f, 0.0f, 0.0f, 0.0f},
112         {0.0f, 0.0f, 0.0f, 0.0f, (float32_t)b0, (float32_t)b1, (float32_t)b2, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f},
113         {0.0f, 0.0f, 0.0f, (float32_t)b0, (float32_t)b1, (float32_t)b2, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f},
114         {0.0f, 0.0f, (float32_t)b0, (float32_t)b1, (float32_t)b2, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f},
115         {0.0f, (float32_t)b0, (float32_t)b1, (float32_t)b2, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f},
116         {(float32_t)b0, (float32_t)b1, (float32_t)b2, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f}
117     };
118 
119     for (int i = 0; i < 12; i++)
120     {
121         coeffs[1][i] += ((float32_t)a1 * coeffs[0][i]);
122         coeffs[2][i] += ((float32_t)a1 * coeffs[1][i]) + ((float32_t)a2 * coeffs[0][i]);
123         coeffs[3][i] += ((float32_t)a1 * coeffs[2][i]) + ((float32_t)a2 * coeffs[1][i]);
124         coeffs[4][i] += ((float32_t)a1 * coeffs[3][i]) + ((float32_t)a2 * coeffs[2][i]);
125         coeffs[5][i] += ((float32_t)a1 * coeffs[4][i]) + ((float32_t)a2 * coeffs[3][i]);
126         coeffs[6][i] += ((float32_t)a1 * coeffs[5][i]) + ((float32_t)a2 * coeffs[4][i]);
127         coeffs[7][i] += ((float32_t)a1 * coeffs[6][i]) + ((float32_t)a2 * coeffs[5][i]);
128 
129         /*
130          * transpose
131          */
132         newCoef->coeffs[i][0] = (float16_t) coeffs[0][i];
133         newCoef->coeffs[i][1] = (float16_t) coeffs[1][i];
134         newCoef->coeffs[i][2] = (float16_t) coeffs[2][i];
135         newCoef->coeffs[i][3] = (float16_t) coeffs[3][i];
136         newCoef->coeffs[i][4] = (float16_t) coeffs[4][i];
137         newCoef->coeffs[i][5] = (float16_t) coeffs[5][i];
138         newCoef->coeffs[i][6] = (float16_t) coeffs[6][i];
139         newCoef->coeffs[i][7] = (float16_t) coeffs[7][i];
140 
141     }
142 }
143 
arm_biquad_cascade_df1_mve_init_f16(arm_biquad_casd_df1_inst_f16 * S,uint8_t numStages,const float16_t * pCoeffs,arm_biquad_mod_coef_f16 * pCoeffsMod,float16_t * pState)144 ARM_DSP_ATTRIBUTE void arm_biquad_cascade_df1_mve_init_f16(arm_biquad_casd_df1_inst_f16 * S,
145                                          uint8_t numStages,
146                                          const float16_t * pCoeffs,
147                                          arm_biquad_mod_coef_f16 * pCoeffsMod,
148                                          float16_t * pState)
149 {
150     arm_biquad_cascade_df1_init_f16(S, numStages, (float16_t *)pCoeffsMod, pState);
151 
152     /* Generate SIMD friendly modified coefs */
153     for (int i = 0; i < numStages; i++)
154     {
155         generateCoefsFastBiquadF16(pCoeffs[0], pCoeffs[1], pCoeffs[2], pCoeffs[3], pCoeffs[4], pCoeffsMod);
156         pCoeffs += 5;
157         pCoeffsMod++;
158     }
159 }
160 
161 #endif
162 
163 /**
164   @} end of BiquadCascadeDF1 group
165  */
166 #endif /* #if defined(ARMfloat16_t_SUPPORTED) */
167