1/* 2 * Copyright (c) 2019 Lexmark International, Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <mem.h> 8#include <arm/armv7-r.dtsi> 9#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h> 10#include <zephyr/dt-bindings/ethernet/xlnx_gem.h> 11 12/ { 13 soc { 14 pinctrl: pinctrl@ff180000 { 15 reg = <0xff180000 0xc80>; 16 compatible = "xlnx,pinctrl-zynqmp"; 17 }; 18 flash0: flash@c0000000 { 19 compatible = "soc-nv-flash"; 20 reg = <0xc0000000 DT_SIZE_M(32)>; 21 }; 22 23 sram0: memory@0 { 24 compatible = "mmio-sram"; 25 reg = <0 DT_SIZE_M(64)>; 26 }; 27 28 ocm: memory@fffc0000 { 29 compatible = "zephyr,memory-region", "xlnx,zynq-ocm"; 30 reg = <0xfffc0000 DT_SIZE_K(256)>; 31 zephyr,memory-region = "OCM"; 32 }; 33 34 uart0: uart@ff000000 { 35 compatible = "xlnx,xuartps"; 36 reg = <0xff000000 0x4c>; 37 status = "disabled"; 38 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL 39 IRQ_DEFAULT_PRIORITY>; 40 interrupt-names = "irq_0"; 41 }; 42 43 uart1: uart@ff010000 { 44 compatible = "xlnx,xuartps"; 45 reg = <0xff010000 0x4c>; 46 status = "disabled"; 47 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL 48 IRQ_DEFAULT_PRIORITY>; 49 interrupt-names = "irq_0"; 50 }; 51 52 ttc0: timer@ff110000 { 53 compatible = "xlnx,ttcps"; 54 status = "disabled"; 55 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL 56 IRQ_DEFAULT_PRIORITY>, 57 <GIC_SPI 37 IRQ_TYPE_LEVEL 58 IRQ_DEFAULT_PRIORITY>, 59 <GIC_SPI 38 IRQ_TYPE_LEVEL 60 IRQ_DEFAULT_PRIORITY>; 61 interrupt-names = "irq_0", "irq_1", "irq_2"; 62 reg = <0xff110000 0x1000>; 63 }; 64 65 ttc1: timer@ff120000 { 66 compatible = "xlnx,ttcps"; 67 status = "disabled"; 68 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL 69 IRQ_DEFAULT_PRIORITY>, 70 <GIC_SPI 40 IRQ_TYPE_LEVEL 71 IRQ_DEFAULT_PRIORITY>, 72 <GIC_SPI 41 IRQ_TYPE_LEVEL 73 IRQ_DEFAULT_PRIORITY>; 74 interrupt-names = "irq_0", "irq_1", "irq_2"; 75 reg = <0xff120000 0x1000>; 76 }; 77 78 ttc2: timer@ff130000 { 79 compatible = "xlnx,ttcps"; 80 status = "disabled"; 81 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL 82 IRQ_DEFAULT_PRIORITY>, 83 <GIC_SPI 43 IRQ_TYPE_LEVEL 84 IRQ_DEFAULT_PRIORITY>, 85 <GIC_SPI 44 IRQ_TYPE_LEVEL 86 IRQ_DEFAULT_PRIORITY>; 87 interrupt-names = "irq_0", "irq_1", "irq_2"; 88 reg = <0xff130000 0x1000>; 89 }; 90 91 ttc3: timer@ff140000 { 92 compatible = "xlnx,ttcps"; 93 status = "disabled"; 94 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL 95 IRQ_DEFAULT_PRIORITY>, 96 <GIC_SPI 46 IRQ_TYPE_LEVEL 97 IRQ_DEFAULT_PRIORITY>, 98 <GIC_SPI 47 IRQ_TYPE_LEVEL 99 IRQ_DEFAULT_PRIORITY>; 100 interrupt-names = "irq_0", "irq_1", "irq_2"; 101 reg = <0xff140000 0x1000>; 102 }; 103 104 gem0: ethernet@ff0b0000 { 105 compatible = "xlnx,gem"; 106 reg = <0xff0b0000 0x1000>, 107 <0xff5e0050 0x4>; 108 status = "disabled"; 109 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL 110 IRQ_DEFAULT_PRIORITY>, 111 <GIC_SPI 58 IRQ_TYPE_LEVEL 112 IRQ_DEFAULT_PRIORITY>; 113 interrupt-names = "irq_0", "irq_1"; 114 mdio-phy-address = <XLNX_GEM_PHY_AUTO_DETECT>; 115 phy-poll-interval = <1000>; 116 link-speed = <XLNX_GEM_LINK_SPEED_100MBIT>; 117 amba-ahb-dbus-width = <XLNX_GEM_AMBA_AHB_DBUS_WIDTH_32BIT>; 118 amba-ahb-burst-length = <XLNX_GEM_AMBA_AHB_BURST_SINGLE>; 119 hw-rx-buffer-size = <XLNX_GEM_HW_RX_BUFFER_SIZE_8KB>; 120 hw-rx-buffer-offset = <0>; 121 hw-tx-buffer-size-full; 122 rx-buffer-descriptors = <32>; 123 tx-buffer-descriptors = <32>; 124 rx-buffer-size = <512>; 125 tx-buffer-size = <512>; 126 discard-rx-fcs; 127 unicast-hash; 128 full-duplex; 129 }; 130 131 gem1: ethernet@ff0c0000 { 132 compatible = "xlnx,gem"; 133 reg = <0xff0c0000 0x1000>, 134 <0xff5e0054 0x4>; 135 status = "disabled"; 136 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL 137 IRQ_DEFAULT_PRIORITY>, 138 <GIC_SPI 60 IRQ_TYPE_LEVEL 139 IRQ_DEFAULT_PRIORITY>; 140 interrupt-names = "irq_0", "irq_1"; 141 mdio-phy-address = <XLNX_GEM_PHY_AUTO_DETECT>; 142 phy-poll-interval = <1000>; 143 link-speed = <XLNX_GEM_LINK_SPEED_100MBIT>; 144 amba-ahb-dbus-width = <XLNX_GEM_AMBA_AHB_DBUS_WIDTH_32BIT>; 145 amba-ahb-burst-length = <XLNX_GEM_AMBA_AHB_BURST_SINGLE>; 146 hw-rx-buffer-size = <XLNX_GEM_HW_RX_BUFFER_SIZE_8KB>; 147 hw-rx-buffer-offset = <0>; 148 hw-tx-buffer-size-full; 149 rx-buffer-descriptors = <32>; 150 tx-buffer-descriptors = <32>; 151 rx-buffer-size = <512>; 152 tx-buffer-size = <512>; 153 discard-rx-fcs; 154 unicast-hash; 155 full-duplex; 156 }; 157 158 gem2: ethernet@ff0d0000 { 159 compatible = "xlnx,gem"; 160 reg = <0xff0d0000 0x1000>, 161 <0xff5e0058 0x4>; 162 status = "disabled"; 163 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL 164 IRQ_DEFAULT_PRIORITY>, 165 <GIC_SPI 62 IRQ_TYPE_LEVEL 166 IRQ_DEFAULT_PRIORITY>; 167 interrupt-names = "irq_0", "irq_1"; 168 mdio-phy-address = <XLNX_GEM_PHY_AUTO_DETECT>; 169 phy-poll-interval = <1000>; 170 link-speed = <XLNX_GEM_LINK_SPEED_100MBIT>; 171 amba-ahb-dbus-width = <XLNX_GEM_AMBA_AHB_DBUS_WIDTH_32BIT>; 172 amba-ahb-burst-length = <XLNX_GEM_AMBA_AHB_BURST_SINGLE>; 173 hw-rx-buffer-size = <XLNX_GEM_HW_RX_BUFFER_SIZE_8KB>; 174 hw-rx-buffer-offset = <0>; 175 hw-tx-buffer-size-full; 176 rx-buffer-descriptors = <32>; 177 tx-buffer-descriptors = <32>; 178 rx-buffer-size = <512>; 179 tx-buffer-size = <512>; 180 discard-rx-fcs; 181 unicast-hash; 182 full-duplex; 183 }; 184 185 gem3: ethernet@ff0e0000 { 186 compatible = "xlnx,gem"; 187 reg = <0xff0e0000 0x1000>, 188 <0xff5e005c 0x4>; 189 status = "disabled"; 190 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL 191 IRQ_DEFAULT_PRIORITY>, 192 <GIC_SPI 64 IRQ_TYPE_LEVEL 193 IRQ_DEFAULT_PRIORITY>; 194 interrupt-names = "irq_0", "irq_1"; 195 mdio-phy-address = <XLNX_GEM_PHY_AUTO_DETECT>; 196 phy-poll-interval = <1000>; 197 link-speed = <XLNX_GEM_LINK_SPEED_100MBIT>; 198 amba-ahb-dbus-width = <XLNX_GEM_AMBA_AHB_DBUS_WIDTH_32BIT>; 199 amba-ahb-burst-length = <XLNX_GEM_AMBA_AHB_BURST_SINGLE>; 200 hw-rx-buffer-size = <XLNX_GEM_HW_RX_BUFFER_SIZE_8KB>; 201 hw-rx-buffer-offset = <0>; 202 hw-tx-buffer-size-full; 203 rx-buffer-descriptors = <32>; 204 tx-buffer-descriptors = <32>; 205 rx-buffer-size = <512>; 206 tx-buffer-size = <512>; 207 discard-rx-fcs; 208 unicast-hash; 209 full-duplex; 210 }; 211 212 psgpio: gpio@ff0a0000 { 213 compatible = "xlnx,ps-gpio"; 214 status = "disabled"; 215 reg = <0xff0a0000 0x1000>; 216 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL 217 IRQ_DEFAULT_PRIORITY>; 218 interrupt-names = "irq_0"; 219 220 #address-cells = <1>; 221 #size-cells = <0>; 222 223 psgpio_bank0: psgpio_bank@0 { 224 compatible = "xlnx,ps-gpio-bank"; 225 reg = <0x0>; 226 gpio-controller; 227 #gpio-cells = <2>; 228 ngpios = <26>; 229 status = "okay"; 230 }; 231 232 psgpio_bank1: psgpio_bank@1 { 233 compatible = "xlnx,ps-gpio-bank"; 234 reg = <0x1>; 235 gpio-controller; 236 #gpio-cells = <2>; 237 ngpios = <26>; 238 status = "okay"; 239 }; 240 241 psgpio_bank2: psgpio_bank@2 { 242 compatible = "xlnx,ps-gpio-bank"; 243 reg = <0x2>; 244 gpio-controller; 245 #gpio-cells = <2>; 246 ngpios = <26>; 247 status = "okay"; 248 }; 249 250 psgpio_bank3: psgpio_bank@3 { 251 compatible = "xlnx,ps-gpio-bank"; 252 reg = <0x3>; 253 gpio-controller; 254 #gpio-cells = <2>; 255 ngpios = <32>; 256 status = "okay"; 257 }; 258 259 psgpio_bank4: psgpio_bank@4 { 260 compatible = "xlnx,ps-gpio-bank"; 261 reg = <0x4>; 262 gpio-controller; 263 #gpio-cells = <2>; 264 ngpios = <32>; 265 status = "okay"; 266 }; 267 268 psgpio_bank5: psgpio_bank@5 { 269 compatible = "xlnx,ps-gpio-bank"; 270 reg = <0x5>; 271 gpio-controller; 272 #gpio-cells = <2>; 273 ngpios = <32>; 274 status = "okay"; 275 }; 276 }; 277 }; 278 279}; 280
