1/* 2 * Copyright (c) 2019 Lexmark International, Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <mem.h> 8#include <arm/armv7-r.dtsi> 9#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h> 10#include <zephyr/dt-bindings/ethernet/xlnx_gem.h> 11 12/ { 13 soc { 14 flash0: flash@c0000000 { 15 compatible = "soc-nv-flash"; 16 reg = <0xc0000000 DT_SIZE_M(32)>; 17 }; 18 19 sram0: memory@0 { 20 compatible = "mmio-sram"; 21 reg = <0 DT_SIZE_M(64)>; 22 }; 23 24 ocm: memory@fffc0000 { 25 compatible = "zephyr,memory-region", "xlnx,zynq-ocm"; 26 reg = <0xfffc0000 DT_SIZE_K(256)>; 27 zephyr,memory-region = "OCM"; 28 }; 29 30 uart0: uart@ff000000 { 31 compatible = "xlnx,xuartps"; 32 reg = <0xff000000 0x4c>; 33 status = "disabled"; 34 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL 35 IRQ_DEFAULT_PRIORITY>; 36 interrupt-names = "irq_0"; 37 }; 38 39 uart1: uart@ff010000 { 40 compatible = "xlnx,xuartps"; 41 reg = <0xff010000 0x4c>; 42 status = "disabled"; 43 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL 44 IRQ_DEFAULT_PRIORITY>; 45 interrupt-names = "irq_0"; 46 }; 47 48 ttc0: timer@ff110000 { 49 compatible = "xlnx,ttcps"; 50 status = "disabled"; 51 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL 52 IRQ_DEFAULT_PRIORITY>, 53 <GIC_SPI 37 IRQ_TYPE_LEVEL 54 IRQ_DEFAULT_PRIORITY>, 55 <GIC_SPI 38 IRQ_TYPE_LEVEL 56 IRQ_DEFAULT_PRIORITY>; 57 interrupt-names = "irq_0", "irq_1", "irq_2"; 58 reg = <0xff110000 0x1000>; 59 }; 60 61 ttc1: timer@ff120000 { 62 compatible = "xlnx,ttcps"; 63 status = "disabled"; 64 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL 65 IRQ_DEFAULT_PRIORITY>, 66 <GIC_SPI 40 IRQ_TYPE_LEVEL 67 IRQ_DEFAULT_PRIORITY>, 68 <GIC_SPI 41 IRQ_TYPE_LEVEL 69 IRQ_DEFAULT_PRIORITY>; 70 interrupt-names = "irq_0", "irq_1", "irq_2"; 71 reg = <0xff120000 0x1000>; 72 }; 73 74 ttc2: timer@ff130000 { 75 compatible = "xlnx,ttcps"; 76 status = "disabled"; 77 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL 78 IRQ_DEFAULT_PRIORITY>, 79 <GIC_SPI 43 IRQ_TYPE_LEVEL 80 IRQ_DEFAULT_PRIORITY>, 81 <GIC_SPI 44 IRQ_TYPE_LEVEL 82 IRQ_DEFAULT_PRIORITY>; 83 interrupt-names = "irq_0", "irq_1", "irq_2"; 84 reg = <0xff130000 0x1000>; 85 }; 86 87 ttc3: timer@ff140000 { 88 compatible = "xlnx,ttcps"; 89 status = "disabled"; 90 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL 91 IRQ_DEFAULT_PRIORITY>, 92 <GIC_SPI 46 IRQ_TYPE_LEVEL 93 IRQ_DEFAULT_PRIORITY>, 94 <GIC_SPI 47 IRQ_TYPE_LEVEL 95 IRQ_DEFAULT_PRIORITY>; 96 interrupt-names = "irq_0", "irq_1", "irq_2"; 97 reg = <0xff140000 0x1000>; 98 }; 99 100 gem0: ethernet@ff0b0000 { 101 compatible = "xlnx,gem"; 102 reg = <0xff0b0000 0x1000>, 103 <0xff5e0050 0x4>; 104 status = "disabled"; 105 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL 106 IRQ_DEFAULT_PRIORITY>, 107 <GIC_SPI 58 IRQ_TYPE_LEVEL 108 IRQ_DEFAULT_PRIORITY>; 109 interrupt-names = "irq_0", "irq_1"; 110 mdio-phy-address = <XLNX_GEM_PHY_AUTO_DETECT>; 111 phy-poll-interval = <1000>; 112 link-speed = <XLNX_GEM_LINK_SPEED_100MBIT>; 113 amba-ahb-dbus-width = <XLNX_GEM_AMBA_AHB_DBUS_WIDTH_32BIT>; 114 amba-ahb-burst-length = <XLNX_GEM_AMBA_AHB_BURST_SINGLE>; 115 hw-rx-buffer-size = <XLNX_GEM_HW_RX_BUFFER_SIZE_8KB>; 116 hw-rx-buffer-offset = <0>; 117 hw-tx-buffer-size-full; 118 rx-buffer-descriptors = <32>; 119 tx-buffer-descriptors = <32>; 120 rx-buffer-size = <512>; 121 tx-buffer-size = <512>; 122 discard-rx-fcs; 123 unicast-hash; 124 full-duplex; 125 }; 126 127 gem1: ethernet@ff0c0000 { 128 compatible = "xlnx,gem"; 129 reg = <0xff0c0000 0x1000>, 130 <0xff5e0054 0x4>; 131 status = "disabled"; 132 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL 133 IRQ_DEFAULT_PRIORITY>, 134 <GIC_SPI 60 IRQ_TYPE_LEVEL 135 IRQ_DEFAULT_PRIORITY>; 136 interrupt-names = "irq_0", "irq_1"; 137 mdio-phy-address = <XLNX_GEM_PHY_AUTO_DETECT>; 138 phy-poll-interval = <1000>; 139 link-speed = <XLNX_GEM_LINK_SPEED_100MBIT>; 140 amba-ahb-dbus-width = <XLNX_GEM_AMBA_AHB_DBUS_WIDTH_32BIT>; 141 amba-ahb-burst-length = <XLNX_GEM_AMBA_AHB_BURST_SINGLE>; 142 hw-rx-buffer-size = <XLNX_GEM_HW_RX_BUFFER_SIZE_8KB>; 143 hw-rx-buffer-offset = <0>; 144 hw-tx-buffer-size-full; 145 rx-buffer-descriptors = <32>; 146 tx-buffer-descriptors = <32>; 147 rx-buffer-size = <512>; 148 tx-buffer-size = <512>; 149 discard-rx-fcs; 150 unicast-hash; 151 full-duplex; 152 }; 153 154 gem2: ethernet@ff0d0000 { 155 compatible = "xlnx,gem"; 156 reg = <0xff0d0000 0x1000>, 157 <0xff5e0058 0x4>; 158 status = "disabled"; 159 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL 160 IRQ_DEFAULT_PRIORITY>, 161 <GIC_SPI 62 IRQ_TYPE_LEVEL 162 IRQ_DEFAULT_PRIORITY>; 163 interrupt-names = "irq_0", "irq_1"; 164 mdio-phy-address = <XLNX_GEM_PHY_AUTO_DETECT>; 165 phy-poll-interval = <1000>; 166 link-speed = <XLNX_GEM_LINK_SPEED_100MBIT>; 167 amba-ahb-dbus-width = <XLNX_GEM_AMBA_AHB_DBUS_WIDTH_32BIT>; 168 amba-ahb-burst-length = <XLNX_GEM_AMBA_AHB_BURST_SINGLE>; 169 hw-rx-buffer-size = <XLNX_GEM_HW_RX_BUFFER_SIZE_8KB>; 170 hw-rx-buffer-offset = <0>; 171 hw-tx-buffer-size-full; 172 rx-buffer-descriptors = <32>; 173 tx-buffer-descriptors = <32>; 174 rx-buffer-size = <512>; 175 tx-buffer-size = <512>; 176 discard-rx-fcs; 177 unicast-hash; 178 full-duplex; 179 }; 180 181 gem3: ethernet@ff0e0000 { 182 compatible = "xlnx,gem"; 183 reg = <0xff0e0000 0x1000>, 184 <0xff5e005c 0x4>; 185 status = "disabled"; 186 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL 187 IRQ_DEFAULT_PRIORITY>, 188 <GIC_SPI 64 IRQ_TYPE_LEVEL 189 IRQ_DEFAULT_PRIORITY>; 190 interrupt-names = "irq_0", "irq_1"; 191 mdio-phy-address = <XLNX_GEM_PHY_AUTO_DETECT>; 192 phy-poll-interval = <1000>; 193 link-speed = <XLNX_GEM_LINK_SPEED_100MBIT>; 194 amba-ahb-dbus-width = <XLNX_GEM_AMBA_AHB_DBUS_WIDTH_32BIT>; 195 amba-ahb-burst-length = <XLNX_GEM_AMBA_AHB_BURST_SINGLE>; 196 hw-rx-buffer-size = <XLNX_GEM_HW_RX_BUFFER_SIZE_8KB>; 197 hw-rx-buffer-offset = <0>; 198 hw-tx-buffer-size-full; 199 rx-buffer-descriptors = <32>; 200 tx-buffer-descriptors = <32>; 201 rx-buffer-size = <512>; 202 tx-buffer-size = <512>; 203 discard-rx-fcs; 204 unicast-hash; 205 full-duplex; 206 }; 207 208 psgpio: gpio@ff0a0000 { 209 compatible = "xlnx,ps-gpio"; 210 status = "disabled"; 211 reg = <0xff0a0000 0x1000>; 212 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL 213 IRQ_DEFAULT_PRIORITY>; 214 interrupt-names = "irq_0"; 215 216 #address-cells = <1>; 217 #size-cells = <0>; 218 219 psgpio_bank0: psgpio_bank@0 { 220 compatible = "xlnx,ps-gpio-bank"; 221 reg = <0x0>; 222 gpio-controller; 223 #gpio-cells = <2>; 224 ngpios = <26>; 225 status = "okay"; 226 }; 227 228 psgpio_bank1: psgpio_bank@1 { 229 compatible = "xlnx,ps-gpio-bank"; 230 reg = <0x1>; 231 gpio-controller; 232 #gpio-cells = <2>; 233 ngpios = <26>; 234 status = "okay"; 235 }; 236 237 psgpio_bank2: psgpio_bank@2 { 238 compatible = "xlnx,ps-gpio-bank"; 239 reg = <0x2>; 240 gpio-controller; 241 #gpio-cells = <2>; 242 ngpios = <26>; 243 status = "okay"; 244 }; 245 246 psgpio_bank3: psgpio_bank@3 { 247 compatible = "xlnx,ps-gpio-bank"; 248 reg = <0x3>; 249 gpio-controller; 250 #gpio-cells = <2>; 251 ngpios = <32>; 252 status = "okay"; 253 }; 254 255 psgpio_bank4: psgpio_bank@4 { 256 compatible = "xlnx,ps-gpio-bank"; 257 reg = <0x4>; 258 gpio-controller; 259 #gpio-cells = <2>; 260 ngpios = <32>; 261 status = "okay"; 262 }; 263 264 psgpio_bank5: psgpio_bank@5 { 265 compatible = "xlnx,ps-gpio-bank"; 266 reg = <0x5>; 267 gpio-controller; 268 #gpio-cells = <2>; 269 ngpios = <32>; 270 status = "okay"; 271 }; 272 }; 273 }; 274}; 275
