1/* 2 * Copyright (c) 2024 Renesas Electronics Corporation 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <mem.h> 8#include <arm/armv8-m.dtsi> 9#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h> 10#include <zephyr/dt-bindings/clock/ra_clock.h> 11#include <zephyr/dt-bindings/pwm/ra_pwm.h> 12#include <freq.h> 13 14/ { 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu@0 { 20 device_type = "cpu"; 21 compatible = "arm,cortex-m33"; 22 reg = <0>; 23 #address-cells = <1>; 24 #size-cells = <1>; 25 26 mpu: mpu@e000ed90 { 27 compatible = "arm,armv8m-mpu"; 28 reg = <0xe000ed90 0x40>; 29 }; 30 }; 31 }; 32 33 soc { 34 interrupt-parent = <&nvic>; 35 36 system: system@4001e000 { 37 compatible = "renesas,ra-system"; 38 reg = <0x4001e000 0x1000>; 39 status = "okay"; 40 }; 41 42 ioport0: gpio@40080000 { 43 compatible = "renesas,ra-gpio-ioport"; 44 reg = <0x40080000 0x20>; 45 port = <0>; 46 gpio-controller; 47 #gpio-cells = <2>; 48 ngpios = <16>; 49 status = "disabled"; 50 }; 51 52 ioport1: gpio@40080020 { 53 compatible = "renesas,ra-gpio-ioport"; 54 reg = <0x40080020 0x20>; 55 port = <1>; 56 gpio-controller; 57 #gpio-cells = <2>; 58 ngpios = <16>; 59 status = "disabled"; 60 }; 61 62 ioport2: gpio@40080040 { 63 compatible = "renesas,ra-gpio-ioport"; 64 reg = <0x40080040 0x20>; 65 port = <2>; 66 gpio-controller; 67 #gpio-cells = <2>; 68 ngpios = <16>; 69 status = "disabled"; 70 }; 71 72 ioport3: gpio@40080060 { 73 compatible = "renesas,ra-gpio-ioport"; 74 reg = <0x40080060 0x20>; 75 port = <3>; 76 gpio-controller; 77 #gpio-cells = <2>; 78 ngpios = <16>; 79 status = "disabled"; 80 }; 81 82 ioport4: gpio@40080080 { 83 compatible = "renesas,ra-gpio-ioport"; 84 reg = <0x40080080 0x20>; 85 port = <4>; 86 gpio-controller; 87 #gpio-cells = <2>; 88 ngpios = <16>; 89 status = "disabled"; 90 }; 91 92 ioport5: gpio@400800a0 { 93 compatible = "renesas,ra-gpio-ioport"; 94 reg = <0x400800a0 0x20>; 95 port = <5>; 96 gpio-controller; 97 #gpio-cells = <2>; 98 ngpios = <16>; 99 status = "disabled"; 100 }; 101 102 pinctrl: pin-contrller@40080800 { 103 compatible = "renesas,ra-pinctrl-pfs"; 104 reg = <0x40080800 0x3c0>; 105 status = "okay"; 106 }; 107 108 sci0: sci0@40118000 { 109 compatible = "renesas,ra-sci"; 110 interrupts = <0 1>, <1 1>, <2 1>, <3 1>; 111 interrupt-names = "rxi", "txi", "tei", "eri"; 112 reg = <0x40118000 0x100>; 113 clocks = <&pclka MSTPB 31>; 114 status = "disabled"; 115 uart { 116 compatible = "renesas,ra-sci-uart"; 117 channel = <0>; 118 status = "disabled"; 119 }; 120 }; 121 122 sci9: sci9@40118900 { 123 compatible = "renesas,ra-sci"; 124 interrupts = <36 1>, <37 1>, <38 1>, <39 1>; 125 interrupt-names = "rxi", "txi", "tei", "eri"; 126 reg = <0x40118900 0x100>; 127 clocks = <&pclka MSTPB 22>; 128 status = "disabled"; 129 uart { 130 compatible = "renesas,ra-sci-uart"; 131 channel = <9>; 132 status = "disabled"; 133 }; 134 }; 135 136 iic0: iic0@4009f000 { 137 compatible = "renesas,ra-iic"; 138 channel = <0>; 139 reg = <0x4009f000 0x100>; 140 status = "disabled"; 141 }; 142 143 iic1: iic1@4009f100 { 144 compatible = "renesas,ra-iic"; 145 channel = <1>; 146 reg = <0x4009f100 0x100>; 147 status = "disabled"; 148 }; 149 150 spi0: spi@4011a000 { 151 compatible = "renesas,ra-spi"; 152 #address-cells = <1>; 153 #size-cells = <0>; 154 channel = <0>; 155 interrupts = <28 1>, <29 1>, <30 1>, <31 1>; 156 interrupt-names = "rxi", "txi", "tei", "eri"; 157 reg = <0x4011a000 0x100>; 158 status = "disabled"; 159 }; 160 161 spi1: spi@4011a100 { 162 compatible = "renesas,ra-spi"; 163 #address-cells = <1>; 164 #size-cells = <0>; 165 channel = <1>; 166 interrupts = <32 1>, <33 1>, <34 1>, <35 1>; 167 interrupt-names = "rxi", "txi", "tei", "eri"; 168 reg = <0x4011a100 0x100>; 169 status = "disabled"; 170 }; 171 172 agt0: agt@400e8000 { 173 compatible = "renesas,ra-agt"; 174 channel = <0>; 175 reg = <0x400e8000 0x100>; 176 renesas,count-source = "AGT_CLOCK_LOCO"; 177 renesas,prescaler = <0>; 178 renesas,resolution = <16>; 179 status = "disabled"; 180 181 counter { 182 compatible = "renesas,ra-agt-counter"; 183 status = "disabled"; 184 }; 185 }; 186 187 agt1: agt@400e8100 { 188 compatible = "renesas,ra-agt"; 189 channel = <1>; 190 reg = <0x400e8100 0x100>; 191 renesas,count-source = "AGT_CLOCK_LOCO"; 192 renesas,prescaler = <0>; 193 renesas,resolution = <16>; 194 status = "disabled"; 195 196 counter { 197 compatible = "renesas,ra-agt-counter"; 198 status = "disabled"; 199 }; 200 }; 201 202 agt2: agt@400e8200 { 203 compatible = "renesas,ra-agt"; 204 channel = <2>; 205 reg = <0x400e8200 0x100>; 206 renesas,count-source = "AGT_CLOCK_LOCO"; 207 renesas,prescaler = <0>; 208 renesas,resolution = <16>; 209 status = "disabled"; 210 211 counter { 212 compatible = "renesas,ra-agt-counter"; 213 status = "disabled"; 214 }; 215 }; 216 217 agt3: agt@400e8300 { 218 compatible = "renesas,ra-agt"; 219 channel = <3>; 220 reg = <0x400e8300 0x100>; 221 renesas,count-source = "AGT_CLOCK_LOCO"; 222 renesas,prescaler = <0>; 223 renesas,resolution = <16>; 224 status = "disabled"; 225 226 counter { 227 compatible = "renesas,ra-agt-counter"; 228 status = "disabled"; 229 }; 230 }; 231 232 agt4: agt@400e8400 { 233 compatible = "renesas,ra-agt"; 234 channel = <4>; 235 reg = <0x400e8400 0x100>; 236 renesas,count-source = "AGT_CLOCK_LOCO"; 237 renesas,prescaler = <0>; 238 renesas,resolution = <16>; 239 status = "disabled"; 240 241 counter { 242 compatible = "renesas,ra-agt-counter"; 243 status = "disabled"; 244 }; 245 }; 246 247 agt5: agt@400e8500 { 248 compatible = "renesas,ra-agt"; 249 channel = <5>; 250 reg = <0x400e8500 0x100>; 251 renesas,count-source = "AGT_CLOCK_LOCO"; 252 renesas,prescaler = <0>; 253 renesas,resolution = <16>; 254 status = "disabled"; 255 256 counter { 257 compatible = "renesas,ra-agt-counter"; 258 status = "disabled"; 259 }; 260 }; 261 262 adc0: adc@40170000 { 263 compatible = "renesas,ra-adc"; 264 interrupts = <40 1>; 265 interrupt-names = "scanend"; 266 reg = <0x40170000 0x100>; 267 #io-channel-cells = <1>; 268 vref-mv = <3300>; 269 status = "disabled"; 270 }; 271 272 adc1: adc@40170200 { 273 compatible = "renesas,ra-adc"; 274 interrupts = <41 1>; 275 interrupt-names = "scanend"; 276 reg = <0x40170200 0x100>; 277 #io-channel-cells = <1>; 278 vref-mv = <3300>; 279 status = "disabled"; 280 }; 281 282 option_setting_ofs: option_setting_ofs@100a100 { 283 compatible = "zephyr,memory-region"; 284 reg = <0x0100a100 0x18>; 285 zephyr,memory-region = "OPTION_SETTING_OFS"; 286 status = "okay"; 287 }; 288 289 option_setting_sas: option_setting_sas@100a134 { 290 compatible = "zephyr,memory-region"; 291 reg = <0x0100a134 0xcc>; 292 zephyr,memory-region = "OPTION_SETTING_SAS"; 293 status = "okay"; 294 }; 295 296 option_setting_s: option_setting_s@100a200 { 297 compatible = "zephyr,memory-region"; 298 reg = <0x0100a200 0x100>; 299 zephyr,memory-region = "OPTION_SETTING_S"; 300 status = "okay"; 301 }; 302 303 port_irq0: external-interrupt@40006000 { 304 compatible = "renesas,ra-external-interrupt"; 305 reg = <0x40006000 0x1>; 306 channel = <0>; 307 renesas,sample-clock-div = <64>; 308 #port-irq-cells = <0>; 309 status = "disabled"; 310 }; 311 312 port_irq1: external-interrupt@40006001 { 313 compatible = "renesas,ra-external-interrupt"; 314 reg = <0x40006001 0x1>; 315 channel = <1>; 316 renesas,sample-clock-div = <64>; 317 #port-irq-cells = <0>; 318 status = "disabled"; 319 }; 320 321 port_irq2: external-interrupt@40006002 { 322 compatible = "renesas,ra-external-interrupt"; 323 reg = <0x40006002 0x1>; 324 channel = <2>; 325 renesas,sample-clock-div = <64>; 326 #port-irq-cells = <0>; 327 status = "disabled"; 328 }; 329 330 port_irq3: external-interrupt@40006003 { 331 compatible = "renesas,ra-external-interrupt"; 332 reg = <0x40006003 0x1>; 333 channel = <3>; 334 renesas,sample-clock-div = <64>; 335 #port-irq-cells = <0>; 336 status = "disabled"; 337 }; 338 339 port_irq4: external-interrupt@40006004 { 340 compatible = "renesas,ra-external-interrupt"; 341 reg = <0x40006004 0x1>; 342 channel = <4>; 343 renesas,sample-clock-div = <64>; 344 #port-irq-cells = <0>; 345 status = "disabled"; 346 }; 347 348 port_irq5: external-interrupt@40006005 { 349 compatible = "renesas,ra-external-interrupt"; 350 reg = <0x40006005 0x1>; 351 channel = <5>; 352 renesas,sample-clock-div = <64>; 353 #port-irq-cells = <0>; 354 status = "disabled"; 355 }; 356 357 port_irq6: external-interrupt@40006006 { 358 compatible = "renesas,ra-external-interrupt"; 359 reg = <0x40006006 0x1>; 360 channel = <6>; 361 renesas,sample-clock-div = <64>; 362 #port-irq-cells = <0>; 363 status = "disabled"; 364 }; 365 366 port_irq7: external-interrupt@40006007 { 367 compatible = "renesas,ra-external-interrupt"; 368 reg = <0x40006007 0x1>; 369 channel = <7>; 370 renesas,sample-clock-div = <64>; 371 #port-irq-cells = <0>; 372 status = "disabled"; 373 }; 374 375 port_irq8: external-interrupt@40006008 { 376 compatible = "renesas,ra-external-interrupt"; 377 reg = <0x40006008 0x1>; 378 channel = <8>; 379 renesas,sample-clock-div = <64>; 380 #port-irq-cells = <0>; 381 status = "disabled"; 382 }; 383 384 port_irq9: external-interrupt@40006009 { 385 compatible = "renesas,ra-external-interrupt"; 386 reg = <0x40006009 0x1>; 387 channel = <9>; 388 renesas,sample-clock-div = <64>; 389 #port-irq-cells = <0>; 390 status = "disabled"; 391 }; 392 393 port_irq10: external-interrupt@4000600a { 394 compatible = "renesas,ra-external-interrupt"; 395 reg = <0x4000600a 0x1>; 396 channel = <10>; 397 renesas,sample-clock-div = <64>; 398 #port-irq-cells = <0>; 399 status = "disabled"; 400 }; 401 402 port_irq11: external-interrupt@4000600b { 403 compatible = "renesas,ra-external-interrupt"; 404 reg = <0x4000600b 0x1>; 405 channel = <11>; 406 renesas,sample-clock-div = <64>; 407 #port-irq-cells = <0>; 408 status = "disabled"; 409 }; 410 411 port_irq12: external-interrupt@4000600c { 412 compatible = "renesas,ra-external-interrupt"; 413 reg = <0x4000600c 0x1>; 414 channel = <12>; 415 renesas,sample-clock-div = <64>; 416 #port-irq-cells = <0>; 417 status = "disabled"; 418 }; 419 420 port_irq13: external-interrupt@4000600d { 421 compatible = "renesas,ra-external-interrupt"; 422 reg = <0x4000600d 0x1>; 423 channel = <13>; 424 renesas,sample-clock-div = <64>; 425 #port-irq-cells = <0>; 426 status = "disabled"; 427 }; 428 429 port_irq14: external-interrupt@4000600e { 430 compatible = "renesas,ra-external-interrupt"; 431 reg = <0x4000600e 0x1>; 432 channel = <14>; 433 renesas,sample-clock-div = <64>; 434 #port-irq-cells = <0>; 435 status = "disabled"; 436 }; 437 438 port_irq15: external-interrupt@4000600f { 439 compatible = "renesas,ra-external-interrupt"; 440 reg = <0x4000600f 0x1>; 441 channel = <15>; 442 renesas,sample-clock-div = <64>; 443 #port-irq-cells = <0>; 444 status = "disabled"; 445 }; 446 447 pwm1: pwm1@40169100 { 448 compatible = "renesas,ra-pwm"; 449 divider = <RA_PWM_SOURCE_DIV_1>; 450 channel = <RA_PWM_CHANNEL_1>; 451 clocks = <&pclkd MSTPE 30>; 452 reg = <0x40169100 0x100>; 453 #pwm-cells = <3>; 454 status = "disabled"; 455 }; 456 457 pwm2: pwm2@40169200 { 458 compatible = "renesas,ra-pwm"; 459 divider = <RA_PWM_SOURCE_DIV_1>; 460 channel = <RA_PWM_CHANNEL_2>; 461 clocks = <&pclkd MSTPE 29>; 462 reg = <0x40169200 0x100>; 463 #pwm-cells = <3>; 464 status = "disabled"; 465 }; 466 467 pwm4: pwm4@40169400 { 468 compatible = "renesas,ra-pwm"; 469 divider = <RA_PWM_SOURCE_DIV_1>; 470 channel = <RA_PWM_CHANNEL_4>; 471 clocks = <&pclkd MSTPE 27>; 472 reg = <0x40169400 0x100>; 473 #pwm-cells = <3>; 474 status = "disabled"; 475 }; 476 477 pwm5: pwm5@40169500 { 478 compatible = "renesas,ra-pwm"; 479 divider = <RA_PWM_SOURCE_DIV_1>; 480 channel = <RA_PWM_CHANNEL_5>; 481 clocks = <&pclkd MSTPE 26>; 482 reg = <0x40169500 0x100>; 483 #pwm-cells = <3>; 484 status = "disabled"; 485 }; 486 }; 487}; 488 489&nvic { 490 arm,num-irq-priority-bits = <4>; 491}; 492
