1/*
2 * Copyright (c) 2024 Renesas Electronics Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm/renesas/ra/ra6/ra6-cm33-common.dtsi>
8#include <zephyr/dt-bindings/clock/ra_clock.h>
9#include <zephyr/dt-bindings/pwm/ra_pwm.h>
10
11/ {
12	soc {
13		sram0: memory@20000000 {
14			compatible = "mmio-sram";
15			reg = <0x20000000 DT_SIZE_K(256)>;
16		};
17
18		sci1: sci1@40118100 {
19			compatible = "renesas,ra-sci";
20			interrupts = <4 1>, <5 1>, <6 1>, <7 1>;
21			interrupt-names = "rxi", "txi", "tei", "eri";
22			reg = <0x40118100 0x100>;
23			clocks = <&pclka MSTPB 30>;
24			status = "disabled";
25			uart {
26				compatible = "renesas,ra-sci-uart";
27				channel = <1>;
28				status = "disabled";
29			};
30		};
31
32		sci2: sci2@40118200 {
33			compatible = "renesas,ra-sci";
34			interrupts = <8 1>, <9 1>, <10 1>, <11 1>;
35			interrupt-names = "rxi", "txi", "tei", "eri";
36			reg = <0x40118200 0x100>;
37			clocks = <&pclka MSTPB 29>;
38			status = "disabled";
39			uart {
40				compatible = "renesas,ra-sci-uart";
41				channel = <2>;
42				status = "disabled";
43			};
44		};
45
46		sci3: sci3@40118300 {
47			compatible = "renesas,ra-sci";
48			interrupts = <12 1>, <13 1>, <14 1>, <15 1>;
49			interrupt-names = "rxi", "txi", "tei", "eri";
50			reg = <0x40118300 0x100>;
51			clocks = <&pclka MSTPB 28>;
52			status = "disabled";
53			uart {
54				compatible = "renesas,ra-sci-uart";
55				channel = <3>;
56				status = "disabled";
57			};
58		};
59
60		sci4: sci4@40118400 {
61			compatible = "renesas,ra-sci";
62			interrupts = <16 1>, <17 1>, <18 1>, <19 1>;
63			interrupt-names = "rxi", "txi", "tei", "eri";
64			reg = <0x40118400 0x100>;
65			clocks = <&pclka MSTPB 27>;
66			status = "disabled";
67			uart {
68				compatible = "renesas,ra-sci-uart";
69				channel = <4>;
70				status = "disabled";
71			};
72		};
73
74		sci5: sci5@40118500 {
75			compatible = "renesas,ra-sci";
76			interrupts = <20 1>, <21 1>, <22 1>, <23 1>;
77			interrupt-names = "rxi", "txi", "tei", "eri";
78			reg = <0x40118500 0x100>;
79			clocks = <&pclka MSTPB 26>;
80			status = "disabled";
81			uart {
82				compatible = "renesas,ra-sci-uart";
83				channel = <5>;
84				status = "disabled";
85			};
86		};
87
88		sci6: sci6@40118600 {
89			compatible = "renesas,ra-sci";
90			interrupts = <24 1>, <25 1>, <26 1>, <27 1>;
91			interrupt-names = "rxi", "txi", "tei", "eri";
92			reg = <0x40118600 0x100>;
93			clocks = <&pclka MSTPB 25>;
94			status = "disabled";
95			uart {
96				compatible = "renesas,ra-sci-uart";
97				channel = <6>;
98				status = "disabled";
99			};
100		};
101
102		sci7: sci7@40118700 {
103			compatible = "renesas,ra-sci";
104			interrupts = <28 1>, <29 1>, <30 1>, <31 1>;
105			interrupt-names = "rxi", "txi", "tei", "eri";
106			reg = <0x40118700 0x100>;
107			clocks = <&pclka MSTPB 24>;
108			status = "disabled";
109			uart {
110				compatible = "renesas,ra-sci-uart";
111				channel = <7>;
112				status = "disabled";
113			};
114		};
115
116		sci8: sci8@40118800 {
117			compatible = "renesas,ra-sci";
118			interrupts = <32 1>, <33 1>, <34 1>, <35 1>;
119			interrupt-names = "rxi", "txi", "tei", "eri";
120			reg = <0x40118800 0x100>;
121			clocks = <&pclka MSTPB 23>;
122			status = "disabled";
123			uart {
124				compatible = "renesas,ra-sci-uart";
125				channel = <8>;
126				status = "disabled";
127			};
128		};
129
130		adc@40170000 {
131			channel-count = <12>;
132			channel-available-mask = <0x33ff>;
133		};
134
135		adc@40170200 {
136			channel-count = <10>;
137			channel-available-mask = <0x7f0007>;
138		};
139
140		ioport6: gpio@400800c0 {
141			compatible = "renesas,ra-gpio-ioport";
142			reg = <0x400800c0 0x20>;
143			port = <6>;
144			gpio-controller;
145			#gpio-cells = <2>;
146			ngpios = <16>;
147			status = "disabled";
148		};
149
150		ioport7: gpio@400800e0 {
151			compatible = "renesas,ra-gpio-ioport";
152			reg = <0x400800e0 0x20>;
153			port = <7>;
154			gpio-controller;
155			#gpio-cells = <2>;
156			ngpios = <16>;
157			status = "disabled";
158		};
159
160		ioport8: gpio@40080100 {
161			compatible = "renesas,ra-gpio-ioport";
162			reg = <0x40080100 0x20>;
163			port = <8>;
164			gpio-controller;
165			#gpio-cells = <2>;
166			ngpios = <16>;
167			status = "disabled";
168		};
169
170		pwm0: pwm0@40169000 {
171			compatible = "renesas,ra-pwm";
172			divider = <RA_PWM_SOURCE_DIV_1>;
173			channel = <RA_PWM_CHANNEL_0>;
174			clocks = <&pclkd MSTPE 31>;
175			reg = <0x40169000 0x100>;
176			#pwm-cells = <3>;
177			status = "disabled";
178		};
179
180		pwm3: pwm3@40169300 {
181			compatible = "renesas,ra-pwm";
182			divider = <RA_PWM_SOURCE_DIV_1>;
183			channel = <RA_PWM_CHANNEL_3>;
184			clocks = <&pclkd MSTPE 28>;
185			reg = <0x40169300 0x100>;
186			#pwm-cells = <3>;
187			status = "disabled";
188		};
189
190		pwm6: pwm6@40169600 {
191			compatible = "renesas,ra-pwm";
192			divider = <RA_PWM_SOURCE_DIV_1>;
193			channel = <RA_PWM_CHANNEL_6>;
194			clocks = <&pclkd MSTPE 25>;
195			reg = <0x40169600 0x100>;
196			#pwm-cells = <3>;
197			status = "disabled";
198		};
199
200		pwm7: pwm7@40169700 {
201			compatible = "renesas,ra-pwm";
202			divider = <RA_PWM_SOURCE_DIV_1>;
203			channel = <RA_PWM_CHANNEL_7>;
204			clocks = <&pclkd MSTPE 24>;
205			reg = <0x40169700 0x100>;
206			#pwm-cells = <3>;
207			status = "disabled";
208		};
209
210		pwm8: pwm8@40169800 {
211			compatible = "renesas,ra-pwm";
212			divider = <RA_PWM_SOURCE_DIV_1>;
213			channel = <RA_PWM_CHANNEL_8>;
214			clocks = <&pclkd MSTPE 23>;
215			reg = <0x40169800 0x100>;
216			#pwm-cells = <3>;
217			status = "disabled";
218		};
219
220		pwm9: pwm9@40169900 {
221			compatible = "renesas,ra-pwm";
222			divider = <RA_PWM_SOURCE_DIV_1>;
223			channel = <RA_PWM_CHANNEL_9>;
224			clocks = <&pclkd MSTPE 22>;
225			reg = <0x40169900 0x100>;
226			#pwm-cells = <3>;
227			status = "disabled";
228		};
229	};
230
231	clocks: clocks {
232		#address-cells = <1>;
233		#size-cells = <1>;
234
235		xtal: clock-main-osc {
236			compatible = "renesas,ra-cgc-external-clock";
237			clock-frequency = <DT_FREQ_M(24)>;
238			#clock-cells = <0>;
239			status = "disabled";
240		};
241
242		hoco: clock-hoco {
243			compatible = "fixed-clock";
244			clock-frequency = <DT_FREQ_M(20)>;
245			#clock-cells = <0>;
246		};
247
248		moco: clock-moco {
249			compatible = "fixed-clock";
250			clock-frequency = <DT_FREQ_M(8)>;
251			#clock-cells = <0>;
252		};
253
254		loco: clock-loco {
255			compatible = "fixed-clock";
256			clock-frequency = <32768>;
257			#clock-cells = <0>;
258		};
259
260		subclk: clock-subclk {
261			compatible = "renesas,ra-cgc-subclk";
262			clock-frequency = <32768>;
263			#clock-cells = <0>;
264			status = "disabled";
265		};
266
267		pll: pll {
268			compatible = "renesas,ra-cgc-pll";
269			#clock-cells = <0>;
270
271			/* PLL */
272			clocks = <&xtal>;
273			div = <3>;
274			mul = <25 0>;
275			status = "disabled";
276		};
277
278		pll2: pll2 {
279			compatible = "renesas,ra-cgc-pll";
280			#clock-cells = <0>;
281
282			/* PLL2 */
283			div = <2>;
284			mul = <20 0>;
285			status = "disabled";
286		};
287
288		pclkblock: pclkblock@40084000 {
289			compatible = "renesas,ra-cgc-pclk-block";
290			reg = <0x40084000 4>, <0x40084004 4>, <0x40084008 4>,
291			      <0x4008400c 4>, <0x40084010 4>;
292			reg-names = "MSTPA", "MSTPB","MSTPC",
293				    "MSTPD", "MSTPE";
294			#clock-cells = <0>;
295			clocks = <&pll>;
296			status = "okay";
297
298			iclk: iclk {
299				compatible = "renesas,ra-cgc-pclk";
300				div = <1>;
301				#clock-cells = <2>;
302				status = "okay";
303			};
304
305			pclka: pclka {
306				compatible = "renesas,ra-cgc-pclk";
307				div = <2>;
308				#clock-cells = <2>;
309				status = "okay";
310			};
311
312			pclkb: pclkb {
313				compatible = "renesas,ra-cgc-pclk";
314				div = <4>;
315				#clock-cells = <2>;
316				status = "okay";
317			};
318
319			pclkc: pclkc {
320				compatible = "renesas,ra-cgc-pclk";
321				div = <4>;
322				#clock-cells = <2>;
323				status = "okay";
324			};
325
326			pclkd: pclkd {
327				compatible = "renesas,ra-cgc-pclk";
328				div = <2>;
329				#clock-cells = <2>;
330				status = "okay";
331			};
332
333			bclk: bclk {
334				compatible = "renesas,ra-cgc-pclk";
335				div = <2>;
336				bclkout: bclkout {
337					compatible = "renesas,ra-cgc-busclk";
338					clk-out-div = <2>;
339					sdclk = <0>;
340					#clock-cells = <0>;
341				};
342				#clock-cells = <2>;
343				status = "okay";
344			};
345
346			fclk: fclk {
347				compatible = "renesas,ra-cgc-pclk";
348				div = <4>;
349				#clock-cells = <2>;
350				status = "okay";
351			};
352
353			clkout: clkout {
354				compatible = "renesas,ra-cgc-pclk";
355				#clock-cells = <2>;
356				status = "disabled";
357			};
358
359			uclk: uclk {
360				compatible = "renesas,ra-cgc-pclk";
361				#clock-cells = <2>;
362				status = "disabled";
363			};
364
365			octaspiclk: octaspiclk {
366				compatible = "renesas,ra-cgc-pclk";
367				#clock-cells = <2>;
368				status = "disabled";
369			};
370		};
371	};
372};
373
374&ioport0 {
375	port-irqs = <&port_irq6 &port_irq7 &port_irq8
376	&port_irq9 &port_irq10 &port_irq11
377	&port_irq12 &port_irq13>;
378	port-irq-names = "port-irq6",
379			 "port-irq7",
380			 "port-irq8",
381			 "port-irq9",
382			 "port-irq10",
383			 "port-irq11",
384			 "port-irq12",
385			 "port-irq13";
386	port-irq6-pins = <0>;
387	port-irq7-pins = <1>;
388	port-irq8-pins = <2>;
389	port-irq9-pins = <4>;
390	port-irq10-pins = <5>;
391	port-irq11-pins = <6>;
392	port-irq12-pins = <8>;
393	port-irq13-pins = <9 15>;
394};
395
396&ioport1 {
397	port-irqs = <&port_irq0 &port_irq1 &port_irq2
398	&port_irq3 &port_irq4>;
399	port-irq-names = "port-irq0",
400			 "port-irq1",
401			 "port-irq2",
402			 "port-irq3",
403			 "port-irq4";
404	port-irq0-pins = <5>;
405	port-irq1-pins = <1 4>;
406	port-irq2-pins = <0>;
407	port-irq3-pins = <10>;
408	port-irq4-pins = <11>;
409};
410
411&ioport2 {
412	port-irqs = <&port_irq0 &port_irq1 &port_irq2
413	&port_irq3>;
414	port-irq-names = "port-irq0",
415			 "port-irq1",
416			 "port-irq2",
417			 "port-irq3";
418	port-irq0-pins = <6>;
419	port-irq1-pins = <5>;
420	port-irq2-pins = <3 13>;
421	port-irq3-pins = <2 12>;
422};
423
424&ioport3 {
425	port-irqs = <&port_irq5 &port_irq6
426	&port_irq8 &port_irq9>;
427	port-irq-names = "port-irq5",
428			 "port-irq6",
429			 "port-irq8",
430			 "port-irq9";
431	port-irq5-pins = <2>;
432	port-irq6-pins = <1>;
433	port-irq8-pins = <5>;
434	port-irq9-pins = <4>;
435};
436
437&ioport4 {
438	port-irqs = <&port_irq0 &port_irq4 &port_irq5
439	&port_irq6 &port_irq7 &port_irq8
440	&port_irq9 &port_irq14 &port_irq15>;
441	port-irq-names = "port-irq0",
442			 "port-irq4",
443			 "port-irq5",
444			 "port-irq6",
445			 "port-irq7",
446			 "port-irq8",
447			 "port-irq9",
448			 "port-irq14",
449			 "port-irq15";
450	port-irq0-pins = <0>;
451	port-irq4-pins = <2 11>;
452	port-irq5-pins = <1 10>;
453	port-irq6-pins = <9>;
454	port-irq7-pins = <8>;
455	port-irq8-pins = <15>;
456	port-irq9-pins = <14>;
457	port-irq14-pins = <3>;
458	port-irq15-pins = <4>;
459};
460
461&ioport5 {
462	port-irqs = <&port_irq11 &port_irq12 &port_irq14
463	&port_irq15>;
464	port-irq-names = "port-irq11",
465			 "port-irq12",
466			 "port-irq14",
467			 "port-irq15";
468	port-irq11-pins = <1>;
469	port-irq12-pins = <2>;
470	port-irq14-pins = <5 12>;
471	port-irq15-pins = <6 11>;
472};
473
474&ioport7 {
475	port-irqs = <&port_irq10 &port_irq11>;
476	port-irq-names = "port-irq10",
477			 "port-irq11";
478	port-irq10-pins = <9>;
479	port-irq11-pins = <8>;
480};
481