1/* 2 * Copyright (c) 2024 Renesas Electronics Corporation 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <mem.h> 8#include <arm/armv8-m.dtsi> 9#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h> 10#include <zephyr/dt-bindings/pwm/ra_pwm.h> 11#include <freq.h> 12 13/ { 14 cpus { 15 #address-cells = <1>; 16 #size-cells = <0>; 17 18 cpu@0 { 19 device_type = "cpu"; 20 compatible = "arm,cortex-m33"; 21 reg = <0>; 22 #address-cells = <1>; 23 #size-cells = <1>; 24 25 mpu: mpu@e000ed90 { 26 compatible = "arm,armv8m-mpu"; 27 reg = <0xe000ed90 0x40>; 28 }; 29 }; 30 }; 31 32 soc { 33 interrupt-parent = <&nvic>; 34 35 system: system@4001e000 { 36 compatible = "renesas,ra-system"; 37 reg = <0x4001e000 0x1000>; 38 status = "okay"; 39 }; 40 41 flash-controller@407e0000 { 42 reg = <0x407e0000 0x10000>; 43 #address-cells = <1>; 44 #size-cells = <1>; 45 }; 46 47 ioport0: gpio@40080000 { 48 compatible = "renesas,ra-gpio-ioport"; 49 reg = <0x40080000 0x20>; 50 port = <0>; 51 gpio-controller; 52 #gpio-cells = <2>; 53 ngpios = <16>; 54 status = "disabled"; 55 }; 56 57 ioport1: gpio@40080020 { 58 compatible = "renesas,ra-gpio-ioport"; 59 reg = <0x40080020 0x20>; 60 port = <1>; 61 gpio-controller; 62 #gpio-cells = <2>; 63 ngpios = <16>; 64 status = "disabled"; 65 }; 66 67 ioport2: gpio@40080040 { 68 compatible = "renesas,ra-gpio-ioport"; 69 reg = <0x40080040 0x20>; 70 port = <2>; 71 gpio-controller; 72 #gpio-cells = <2>; 73 ngpios = <16>; 74 status = "disabled"; 75 }; 76 77 ioport3: gpio@40080060 { 78 compatible = "renesas,ra-gpio-ioport"; 79 reg = <0x40080060 0x20>; 80 port = <3>; 81 gpio-controller; 82 #gpio-cells = <2>; 83 ngpios = <16>; 84 status = "disabled"; 85 }; 86 87 ioport4: gpio@40080080 { 88 compatible = "renesas,ra-gpio-ioport"; 89 reg = <0x40080080 0x20>; 90 port = <4>; 91 gpio-controller; 92 #gpio-cells = <2>; 93 ngpios = <16>; 94 status = "disabled"; 95 }; 96 97 ioport5: gpio@400800a0 { 98 compatible = "renesas,ra-gpio-ioport"; 99 reg = <0x400800a0 0x20>; 100 port = <5>; 101 gpio-controller; 102 #gpio-cells = <2>; 103 ngpios = <16>; 104 status = "disabled"; 105 }; 106 107 pinctrl: pin-controller@40080800 { 108 compatible = "renesas,ra-pinctrl-pfs"; 109 reg = <0x40080800 0x3c0>; 110 status = "okay"; 111 }; 112 113 sci0: sci0@40118000 { 114 compatible = "renesas,ra-sci"; 115 interrupts = <0 1>, <1 1>, <2 1>, <3 1>; 116 interrupt-names = "rxi", "txi", "tei", "eri"; 117 reg = <0x40118000 0x100>; 118 clocks = <&pclka MSTPB 31>; 119 status = "disabled"; 120 uart { 121 compatible = "renesas,ra-sci-uart"; 122 channel = <0>; 123 status = "disabled"; 124 }; 125 }; 126 127 sci9: sci9@40118900 { 128 compatible = "renesas,ra-sci"; 129 interrupts = <36 1>, <37 1>, <38 1>, <39 1>; 130 interrupt-names = "rxi", "txi", "tei", "eri"; 131 reg = <0x40118900 0x100>; 132 clocks = <&pclka MSTPB 22>; 133 status = "disabled"; 134 uart { 135 compatible = "renesas,ra-sci-uart"; 136 channel = <9>; 137 status = "disabled"; 138 }; 139 }; 140 141 spi0: spi@4011a000 { 142 compatible = "renesas,ra-spi"; 143 #address-cells = <1>; 144 #size-cells = <0>; 145 channel = <0>; 146 interrupts = <28 1>, <29 1>, <30 1>, <31 1>; 147 interrupt-names = "rxi", "txi", "tei", "eri"; 148 reg = <0x4011a000 0x100>; 149 status = "disabled"; 150 }; 151 152 spi1: spi@4011a100 { 153 compatible = "renesas,ra-spi"; 154 #address-cells = <1>; 155 #size-cells = <0>; 156 channel = <1>; 157 reg = <0x4011a100 0x100>; 158 status = "disabled"; 159 }; 160 161 agt0: agt@400e8000 { 162 compatible = "renesas,ra-agt"; 163 channel = <0>; 164 reg = <0x400e8000 0x100>; 165 renesas,count-source = "AGT_CLOCK_LOCO"; 166 renesas,prescaler = <0>; 167 renesas,resolution = <16>; 168 status = "disabled"; 169 170 counter { 171 compatible = "renesas,ra-agt-counter"; 172 status = "disabled"; 173 }; 174 }; 175 176 agt1: agt@400e8100 { 177 compatible = "renesas,ra-agt"; 178 channel = <1>; 179 reg = <0x400e8100 0x100>; 180 renesas,count-source = "AGT_CLOCK_LOCO"; 181 renesas,prescaler = <0>; 182 renesas,resolution = <16>; 183 status = "disabled"; 184 185 counter { 186 compatible = "renesas,ra-agt-counter"; 187 status = "disabled"; 188 }; 189 }; 190 191 agt2: agt@400e8200 { 192 compatible = "renesas,ra-agt"; 193 channel = <2>; 194 reg = <0x400e8200 0x100>; 195 renesas,count-source = "AGT_CLOCK_LOCO"; 196 renesas,prescaler = <0>; 197 renesas,resolution = <16>; 198 status = "disabled"; 199 200 counter { 201 compatible = "renesas,ra-agt-counter"; 202 status = "disabled"; 203 }; 204 }; 205 206 agt3: agt@400e8300 { 207 compatible = "renesas,ra-agt"; 208 channel = <3>; 209 reg = <0x400e8300 0x100>; 210 renesas,count-source = "AGT_CLOCK_LOCO"; 211 renesas,prescaler = <0>; 212 renesas,resolution = <16>; 213 status = "disabled"; 214 215 counter { 216 compatible = "renesas,ra-agt-counter"; 217 status = "disabled"; 218 }; 219 }; 220 221 agt4: agt@400e8400 { 222 compatible = "renesas,ra-agt"; 223 channel = <4>; 224 reg = <0x400e8400 0x100>; 225 renesas,count-source = "AGT_CLOCK_LOCO"; 226 renesas,prescaler = <0>; 227 renesas,resolution = <16>; 228 status = "disabled"; 229 230 counter { 231 compatible = "renesas,ra-agt-counter"; 232 status = "disabled"; 233 }; 234 }; 235 236 agt5: agt@400e8500 { 237 compatible = "renesas,ra-agt"; 238 channel = <5>; 239 reg = <0x400e8500 0x100>; 240 renesas,count-source = "AGT_CLOCK_LOCO"; 241 renesas,prescaler = <0>; 242 renesas,resolution = <16>; 243 status = "disabled"; 244 245 counter { 246 compatible = "renesas,ra-agt-counter"; 247 status = "disabled"; 248 }; 249 }; 250 251 adc0: adc@40170000 { 252 compatible = "renesas,ra-adc"; 253 interrupts = <40 1>; 254 interrupt-names = "scanend"; 255 reg = <0x40170000 0x100>; 256 #io-channel-cells = <1>; 257 vref-mv = <3300>; 258 status = "disabled"; 259 }; 260 261 adc1: adc@40170200 { 262 compatible = "renesas,ra-adc"; 263 interrupts = <41 1>; 264 interrupt-names = "scanend"; 265 reg = <0x40170200 0x100>; 266 #io-channel-cells = <1>; 267 vref-mv = <3300>; 268 status = "disabled"; 269 }; 270 271 iic0: iic0@4009f000 { 272 compatible = "renesas,ra-iic"; 273 channel = <0>; 274 reg = <0x4009f000 0x100>; 275 status = "disabled"; 276 }; 277 278 iic1: iic1@4009f100 { 279 compatible = "renesas,ra-iic"; 280 channel = <1>; 281 reg = <0x4009f100 0x100>; 282 status = "disabled"; 283 }; 284 285 option_setting_ofs: option_setting_ofs@100a100 { 286 compatible = "zephyr,memory-region"; 287 reg = <0x0100a100 0x18>; 288 zephyr,memory-region = "OPTION_SETTING_OFS"; 289 status = "okay"; 290 }; 291 292 option_setting_sas: option_setting_sas@100a134 { 293 compatible = "zephyr,memory-region"; 294 reg = <0x0100a134 0xcc>; 295 zephyr,memory-region = "OPTION_SETTING_SAS"; 296 status = "okay"; 297 }; 298 299 option_setting_s: option_setting_s@100a200 { 300 compatible = "zephyr,memory-region"; 301 reg = <0x0100a200 0x100>; 302 zephyr,memory-region = "OPTION_SETTING_S"; 303 status = "okay"; 304 }; 305 306 port_irq0: external-interrupt@40006000 { 307 compatible = "renesas,ra-external-interrupt"; 308 reg = <0x40006000 0x1>; 309 channel = <0>; 310 renesas,sample-clock-div = <64>; 311 #port-irq-cells = <0>; 312 status = "disabled"; 313 }; 314 315 port_irq1: external-interrupt@40006001 { 316 compatible = "renesas,ra-external-interrupt"; 317 reg = <0x40006001 0x1>; 318 channel = <1>; 319 renesas,sample-clock-div = <64>; 320 #port-irq-cells = <0>; 321 status = "disabled"; 322 }; 323 324 port_irq2: external-interrupt@40006002 { 325 compatible = "renesas,ra-external-interrupt"; 326 reg = <0x40006002 0x1>; 327 channel = <2>; 328 renesas,sample-clock-div = <64>; 329 #port-irq-cells = <0>; 330 status = "disabled"; 331 }; 332 333 port_irq3: external-interrupt@40006003 { 334 compatible = "renesas,ra-external-interrupt"; 335 reg = <0x40006003 0x1>; 336 channel = <3>; 337 renesas,sample-clock-div = <64>; 338 #port-irq-cells = <0>; 339 status = "disabled"; 340 }; 341 342 port_irq4: external-interrupt@40006004 { 343 compatible = "renesas,ra-external-interrupt"; 344 reg = <0x40006004 0x1>; 345 channel = <4>; 346 renesas,sample-clock-div = <64>; 347 #port-irq-cells = <0>; 348 status = "disabled"; 349 }; 350 351 port_irq5: external-interrupt@40006005 { 352 compatible = "renesas,ra-external-interrupt"; 353 reg = <0x40006005 0x1>; 354 channel = <5>; 355 renesas,sample-clock-div = <64>; 356 #port-irq-cells = <0>; 357 status = "disabled"; 358 }; 359 360 port_irq6: external-interrupt@40006006 { 361 compatible = "renesas,ra-external-interrupt"; 362 reg = <0x40006006 0x1>; 363 channel = <6>; 364 renesas,sample-clock-div = <64>; 365 #port-irq-cells = <0>; 366 status = "disabled"; 367 }; 368 369 port_irq7: external-interrupt@40006007 { 370 compatible = "renesas,ra-external-interrupt"; 371 reg = <0x40006007 0x1>; 372 channel = <7>; 373 renesas,sample-clock-div = <64>; 374 #port-irq-cells = <0>; 375 status = "disabled"; 376 }; 377 378 port_irq8: external-interrupt@40006008 { 379 compatible = "renesas,ra-external-interrupt"; 380 reg = <0x40006008 0x1>; 381 channel = <8>; 382 renesas,sample-clock-div = <64>; 383 #port-irq-cells = <0>; 384 status = "disabled"; 385 }; 386 387 port_irq9: external-interrupt@40006009 { 388 compatible = "renesas,ra-external-interrupt"; 389 reg = <0x40006009 0x1>; 390 channel = <9>; 391 renesas,sample-clock-div = <64>; 392 #port-irq-cells = <0>; 393 status = "disabled"; 394 }; 395 396 port_irq10: external-interrupt@4000600a { 397 compatible = "renesas,ra-external-interrupt"; 398 reg = <0x4000600a 0x1>; 399 channel = <10>; 400 renesas,sample-clock-div = <64>; 401 #port-irq-cells = <0>; 402 status = "disabled"; 403 }; 404 405 port_irq11: external-interrupt@4000600b { 406 compatible = "renesas,ra-external-interrupt"; 407 reg = <0x4000600b 0x1>; 408 channel = <11>; 409 renesas,sample-clock-div = <64>; 410 #port-irq-cells = <0>; 411 status = "disabled"; 412 }; 413 414 port_irq12: external-interrupt@4000600c { 415 compatible = "renesas,ra-external-interrupt"; 416 reg = <0x4000600c 0x1>; 417 channel = <12>; 418 renesas,sample-clock-div = <64>; 419 #port-irq-cells = <0>; 420 status = "disabled"; 421 }; 422 423 port_irq13: external-interrupt@4000600d { 424 compatible = "renesas,ra-external-interrupt"; 425 reg = <0x4000600d 0x1>; 426 channel = <13>; 427 renesas,sample-clock-div = <64>; 428 #port-irq-cells = <0>; 429 status = "disabled"; 430 }; 431 432 port_irq14: external-interrupt@4000600e { 433 compatible = "renesas,ra-external-interrupt"; 434 reg = <0x4000600e 0x1>; 435 channel = <14>; 436 renesas,sample-clock-div = <64>; 437 #port-irq-cells = <0>; 438 status = "disabled"; 439 }; 440 441 port_irq15: external-interrupt@4000600f { 442 compatible = "renesas,ra-external-interrupt"; 443 reg = <0x4000600f 0x1>; 444 channel = <15>; 445 renesas,sample-clock-div = <64>; 446 #port-irq-cells = <0>; 447 status = "disabled"; 448 }; 449 450 pwm0: pwm0@40169000 { 451 compatible = "renesas,ra-pwm"; 452 divider = <RA_PWM_SOURCE_DIV_1>; 453 channel = <RA_PWM_CHANNEL_0>; 454 clocks = <&pclkd MSTPE 31>; 455 reg = <0x40169000 0x100>; 456 #pwm-cells = <3>; 457 status = "disabled"; 458 }; 459 460 pwm1: pwm1@40169100 { 461 compatible = "renesas,ra-pwm"; 462 divider = <RA_PWM_SOURCE_DIV_1>; 463 channel = <RA_PWM_CHANNEL_1>; 464 clocks = <&pclkd MSTPE 30>; 465 reg = <0x40169100 0x100>; 466 #pwm-cells = <3>; 467 status = "disabled"; 468 }; 469 470 pwm4: pwm4@40169400 { 471 compatible = "renesas,ra-pwm"; 472 divider = <RA_PWM_SOURCE_DIV_1>; 473 channel = <RA_PWM_CHANNEL_4>; 474 clocks = <&pclkd MSTPE 27>; 475 reg = <0x40169400 0x100>; 476 #pwm-cells = <3>; 477 status = "disabled"; 478 }; 479 480 pwm5: pwm5@40169500 { 481 compatible = "renesas,ra-pwm"; 482 divider = <RA_PWM_SOURCE_DIV_1>; 483 channel = <RA_PWM_CHANNEL_5>; 484 clocks = <&pclkd MSTPE 26>; 485 reg = <0x40169500 0x100>; 486 #pwm-cells = <3>; 487 status = "disabled"; 488 }; 489 }; 490}; 491 492&nvic { 493 arm,num-irq-priority-bits = <4>; 494}; 495
