1/*
2 * Copyright (c) 2024 Renesas Electronics Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm/renesas/ra/ra4/ra4-cm33-common.dtsi>
8#include <zephyr/dt-bindings/clock/ra_clock.h>
9#include <zephyr/dt-bindings/pwm/ra_pwm.h>
10
11/delete-node/ &spi1;
12
13/delete-node/ &adc1;
14
15/ {
16	soc {
17		sram0: memory@20000000 {
18			compatible = "mmio-sram";
19			reg = <0x20000000 DT_SIZE_K(128)>;
20		};
21
22		ioport6: gpio@400800c0 {
23			compatible = "renesas,ra-gpio-ioport";
24			reg = <0x400800c0 0x20>;
25			port = <6>;
26			gpio-controller;
27			#gpio-cells = <2>;
28			ngpios = <16>;
29			status = "disabled";
30		};
31
32		ioport7: gpio@400800e0 {
33			compatible = "renesas,ra-gpio-ioport";
34			reg = <0x400800e0 0x20>;
35			port = <7>;
36			gpio-controller;
37			#gpio-cells = <2>;
38			ngpios = <16>;
39			status = "disabled";
40		};
41
42		sci1: sci1@40118100 {
43			compatible = "renesas,ra-sci";
44			interrupts = <4 1>, <5 1>, <6 1>, <7 1>;
45			interrupt-names = "rxi", "txi", "tei", "eri";
46			reg = <0x40118100 0x100>;
47			clocks = <&pclka MSTPB 30>;
48			status = "disabled";
49			uart {
50				compatible = "renesas,ra-sci-uart";
51				channel = <1>;
52				status = "disabled";
53			};
54		};
55
56		sci2: sci2@40118200 {
57			compatible = "renesas,ra-sci";
58			interrupts = <8 1>, <9 1>, <10 1>, <11 1>;
59			interrupt-names = "rxi", "txi", "tei", "eri";
60			reg = <0x40118200 0x100>;
61			clocks = <&pclka MSTPB 29>;
62			status = "disabled";
63			uart {
64				compatible = "renesas,ra-sci-uart";
65				channel = <2>;
66				status = "disabled";
67			};
68		};
69
70		sci3: sci3@40118300 {
71			compatible = "renesas,ra-sci";
72			interrupts = <12 1>, <13 1>, <14 1>, <15 1>;
73			interrupt-names = "rxi", "txi", "tei", "eri";
74			reg = <0x40118300 0x100>;
75			clocks = <&pclka MSTPB 28>;
76			status = "disabled";
77			uart {
78				compatible = "renesas,ra-sci-uart";
79				channel = <3>;
80				status = "disabled";
81			};
82		};
83
84		sci4: sci4@40118400 {
85			compatible = "renesas,ra-sci";
86			interrupts = <16 1>, <17 1>, <18 1>, <19 1>;
87			interrupt-names = "rxi", "txi", "tei", "eri";
88			reg = <0x40118400 0x100>;
89			clocks = <&pclka MSTPB 27>;
90			status = "disabled";
91			uart {
92				compatible = "renesas,ra-sci-uart";
93				channel = <4>;
94				status = "disabled";
95			};
96		};
97
98		adc@40170000 {
99			channel-count = <13>;
100			channel-available-mask = <0x139ff>;
101		};
102
103		pwm2: pwm2@40169200 {
104			compatible = "renesas,ra-pwm";
105			divider = <RA_PWM_SOURCE_DIV_1>;
106			channel = <RA_PWM_CHANNEL_2>;
107			clocks = <&pclkd MSTPE 29>;
108			reg = <0x40169200 0x100>;
109			#pwm-cells = <3>;
110			status = "disabled";
111		};
112
113		pwm3: pwm3@40169300 {
114			compatible = "renesas,ra-pwm";
115			divider = <RA_PWM_SOURCE_DIV_1>;
116			channel = <RA_PWM_CHANNEL_3>;
117			clocks = <&pclkd MSTPE 28>;
118			reg = <0x40169300 0x100>;
119			#pwm-cells = <3>;
120			status = "disabled";
121		};
122
123		pwm6: pwm6@40169600 {
124			compatible = "renesas,ra-pwm";
125			divider = <RA_PWM_SOURCE_DIV_1>;
126			channel = <RA_PWM_CHANNEL_6>;
127			clocks = <&pclkd MSTPE 25>;
128			reg = <0x40169600 0x100>;
129			#pwm-cells = <3>;
130			status = "disabled";
131		};
132
133		pwm7: pwm7@40169700 {
134			compatible = "renesas,ra-pwm";
135			divider = <RA_PWM_SOURCE_DIV_1>;
136			channel = <RA_PWM_CHANNEL_7>;
137			clocks = <&pclkd MSTPE 24>;
138			reg = <0x40169700 0x100>;
139			#pwm-cells = <3>;
140			status = "disabled";
141		};
142	};
143
144	clocks: clocks {
145		#address-cells = <1>;
146		#size-cells = <1>;
147
148		xtal: clock-main-osc {
149			compatible = "renesas,ra-cgc-external-clock";
150			clock-frequency = <DT_FREQ_M(24)>;
151			#clock-cells = <0>;
152			status = "disabled";
153		};
154
155		hoco: clock-hoco {
156			compatible = "fixed-clock";
157			clock-frequency = <DT_FREQ_M(20)>;
158			#clock-cells = <0>;
159		};
160
161		moco: clock-moco {
162			compatible = "fixed-clock";
163			clock-frequency = <DT_FREQ_M(8)>;
164			#clock-cells = <0>;
165		};
166
167		loco: clock-loco {
168			compatible = "fixed-clock";
169			clock-frequency = <32768>;
170			#clock-cells = <0>;
171		};
172
173		subclk: clock-subclk {
174			compatible = "renesas,ra-cgc-subclk";
175			clock-frequency = <32768>;
176			#clock-cells = <0>;
177			status = "disabled";
178		};
179
180		pll: pll {
181			compatible = "renesas,ra-cgc-pll";
182			#clock-cells = <0>;
183
184			/* PLL */
185			clocks = <&xtal>;
186			div = <3>;
187			mul = <25 0>;
188			status = "disabled";
189		};
190
191		pll2: pll2 {
192			compatible = "renesas,ra-cgc-pll";
193			#clock-cells = <0>;
194
195			/* PLL */
196			div = <2>;
197			mul = <20 0>;
198			status = "disabled";
199		};
200
201		pclkblock: pclkblock@40084000 {
202			compatible = "renesas,ra-cgc-pclk-block";
203			reg = <0x40084000 4>, <0x40084004 4>, <0x40084008 4>,
204			      <0x4008400c 4>, <0x40084010 4>;
205			reg-names = "MSTPA", "MSTPB","MSTPC",
206				    "MSTPD", "MSTPE";
207			#clock-cells = <0>;
208			clocks = <&pll>;
209			status = "okay";
210
211			iclk: iclk {
212				compatible = "renesas,ra-cgc-pclk";
213				div = <2>;
214				#clock-cells = <2>;
215				status = "okay";
216			};
217
218			pclka: pclka {
219				compatible = "renesas,ra-cgc-pclk";
220				div = <2>;
221				#clock-cells = <2>;
222				status = "okay";
223			};
224
225			pclkb: pclkb {
226				compatible = "renesas,ra-cgc-pclk";
227				div = <4>;
228				#clock-cells = <2>;
229				status = "okay";
230			};
231
232			pclkc: pclkc {
233				compatible = "renesas,ra-cgc-pclk";
234				div = <4>;
235				#clock-cells = <2>;
236				status = "okay";
237			};
238
239			pclkd: pclkd {
240				compatible = "renesas,ra-cgc-pclk";
241				div = <2>;
242				#clock-cells = <2>;
243				status = "okay";
244			};
245
246			fclk: fclk {
247				compatible = "renesas,ra-cgc-pclk";
248				div = <4>;
249				#clock-cells = <2>;
250				status = "okay";
251			};
252
253			clkout: clkout {
254				compatible = "renesas,ra-cgc-pclk";
255				#clock-cells = <2>;
256				status = "disabled";
257			};
258
259			uclk: uclk {
260				compatible = "renesas,ra-cgc-pclk";
261				#clock-cells = <2>;
262				status = "disabled";
263			};
264		};
265	};
266};
267
268&ioport0 {
269	port-irqs = <&port_irq6 &port_irq7 &port_irq8
270	&port_irq9 &port_irq10 &port_irq11
271	&port_irq12 &port_irq13>;
272	port-irq-names = "port-irq6",
273			 "port-irq7",
274			 "port-irq8",
275			 "port-irq9",
276			 "port-irq10",
277			 "port-irq11",
278			 "port-irq12",
279			 "port-irq13";
280	port-irq6-pins = <0>;
281	port-irq7-pins = <1>;
282	port-irq8-pins = <2>;
283	port-irq9-pins = <4>;
284	port-irq10-pins = <5>;
285	port-irq11-pins = <6>;
286	port-irq12-pins = <8>;
287	port-irq13-pins = <15>;
288};
289
290&ioport1 {
291	port-irqs = <&port_irq0 &port_irq1 &port_irq2
292	&port_irq3 &port_irq4>;
293	port-irq-names = "port-irq0",
294			 "port-irq1",
295			 "port-irq2",
296			 "port-irq3",
297			 "port-irq4";
298	port-irq0-pins = <5>;
299	port-irq1-pins = <1 4>;
300	port-irq2-pins = <0>;
301	port-irq3-pins = <10>;
302	port-irq4-pins = <11>;
303};
304
305&ioport2 {
306	port-irqs = <&port_irq0 &port_irq1 &port_irq2
307	&port_irq3>;
308	port-irq-names = "port-irq0",
309			 "port-irq1",
310			 "port-irq2",
311			 "port-irq3";
312	port-irq0-pins = <6>;
313	port-irq1-pins = <5>;
314	port-irq2-pins = <13>;
315	port-irq3-pins = <12>;
316};
317
318&ioport3 {
319	port-irqs = <&port_irq5 &port_irq6
320	&port_irq8 &port_irq9>;
321	port-irq-names = "port-irq5",
322			 "port-irq6",
323			 "port-irq8",
324			 "port-irq9";
325	port-irq5-pins = <2>;
326	port-irq6-pins = <1>;
327	port-irq8-pins = <5>;
328	port-irq9-pins = <4>;
329};
330
331&ioport4 {
332	port-irqs = <&port_irq0 &port_irq4 &port_irq5
333	&port_irq6 &port_irq7 &port_irq8
334	&port_irq9 &port_irq14 &port_irq15>;
335	port-irq-names = "port-irq0",
336			 "port-irq4",
337			 "port-irq5",
338			 "port-irq6",
339			 "port-irq7",
340			 "port-irq8",
341			 "port-irq9",
342			 "port-irq14",
343			 "port-irq15";
344	port-irq0-pins = <0>;
345	port-irq4-pins = <2 11>;
346	port-irq5-pins = <1 10>;
347	port-irq6-pins = <9>;
348	port-irq7-pins = <8>;
349	port-irq8-pins = <15>;
350	port-irq9-pins = <14>;
351	port-irq14-pins = <3>;
352	port-irq15-pins = <4>;
353};
354
355&ioport5 {
356	port-irqs = <&port_irq11 &port_irq12 &port_irq14>;
357	port-irq-names = "port-irq11",
358			 "port-irq12",
359			 "port-irq14";
360	port-irq11-pins = <1>;
361	port-irq12-pins = <2>;
362	port-irq14-pins = <5>;
363};
364
365&ioport7 {
366	port-irqs = <&port_irq11>;
367	port-irq-names = "port-irq11";
368	port-irq11-pins = <8>;
369};
370