1/* 2 * Copyright 2022-2024 NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <mem.h> 8#include <arm/armv8-r.dtsi> 9#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h> 10#include <zephyr/dt-bindings/clock/nxp_s32z2_clock.h> 11#include <zephyr/dt-bindings/i2c/i2c.h> 12 13/ { 14 cpus { 15 #address-cells = <1>; 16 #size-cells = <0>; 17 18 cpu@0 { 19 device_type = "cpu"; 20 compatible = "arm,cortex-r52"; 21 reg = <0>; 22 }; 23 24 cpu@1 { 25 device_type = "cpu"; 26 compatible = "arm,cortex-r52"; 27 reg = <1>; 28 }; 29 30 cpu@2 { 31 device_type = "cpu"; 32 compatible = "arm,cortex-r52"; 33 reg = <2>; 34 }; 35 36 cpu@3 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-r52"; 39 reg = <3>; 40 }; 41 42 cpu@4 { 43 device_type = "cpu"; 44 compatible = "arm,cortex-r52"; 45 reg = <4>; 46 }; 47 48 cpu@5 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-r52"; 51 reg = <5>; 52 }; 53 54 cpu@6 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-r52"; 57 reg = <6>; 58 }; 59 60 cpu@7 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-r52"; 63 reg = <7>; 64 }; 65 }; 66 67 arch_timer: timer { 68 compatible = "arm,armv8_timer"; 69 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 70 <GIC_PPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 71 <GIC_PPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 72 <GIC_PPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 73 interrupt-parent = <&gic>; 74 }; 75 76 /* Dummy pinctrl node, filled with pin mux options at board level */ 77 pinctrl: pinctrl { 78 compatible = "nxp,s32ze-pinctrl"; 79 status = "okay"; 80 }; 81 82 soc { 83 interrupt-parent = <&gic>; 84 85 clock: clock-controller@40030000 { 86 compatible = "nxp,s32-clock"; 87 reg = <0x40030000 0x10000>, 88 <0x40200000 0x10000>, 89 <0x40210000 0x10000>, 90 <0x40220000 0x10000>, 91 <0x40260000 0x10000>, 92 <0x40270000 0x10000>, 93 <0x40830000 0x10000>, 94 <0x41030000 0x10000>, 95 <0x41830000 0x10000>, 96 <0x42030000 0x10000>, 97 <0x42830000 0x10000>, 98 <0x44030000 0x10000>, 99 <0x440a0000 0x10000>; 100 #clock-cells = <1>; 101 status = "okay"; 102 }; 103 104 gic: interrupt-controller@47800000 { 105 compatible = "arm,gic-v3", "arm,gic"; 106 reg = <0x47800000 0x10000>, 107 <0x47900000 0x80000>; 108 #address-cells = <0>; 109 interrupt-controller; 110 #interrupt-cells = <4>; 111 status = "okay"; 112 }; 113 114 dram0: memory@31780000 { 115 compatible = "mmio-sram"; 116 reg = <0x31780000 DT_SIZE_M(1)>; 117 }; 118 119 dram1: memory@35780000 { 120 compatible = "mmio-sram"; 121 reg = <0x35780000 DT_SIZE_M(1)>; 122 }; 123 124 uart0: uart@40170000 { 125 compatible = "nxp,s32-linflexd"; 126 reg = <0x40170000 0x1000>; 127 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 128 status = "disabled"; 129 }; 130 131 uart1: uart@40180000 { 132 compatible = "nxp,s32-linflexd"; 133 reg = <0x40180000 0x1000>; 134 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 135 status = "disabled"; 136 }; 137 138 uart2: uart@40190000 { 139 compatible = "nxp,s32-linflexd"; 140 reg = <0x40190000 0x1000>; 141 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 142 status = "disabled"; 143 }; 144 145 uart3: uart@40970000 { 146 compatible = "nxp,s32-linflexd"; 147 reg = <0x40970000 0x1000>; 148 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 149 status = "disabled"; 150 }; 151 152 uart4: uart@40980000 { 153 compatible = "nxp,s32-linflexd"; 154 reg = <0x40980000 0x1000>; 155 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 156 status = "disabled"; 157 }; 158 159 uart5: uart@40990000 { 160 compatible = "nxp,s32-linflexd"; 161 reg = <0x40990000 0x1000>; 162 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 163 status = "disabled"; 164 }; 165 166 uart6: uart@42170000 { 167 compatible = "nxp,s32-linflexd"; 168 reg = <0x42170000 0x1000>; 169 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 170 status = "disabled"; 171 }; 172 173 uart7: uart@42180000 { 174 compatible = "nxp,s32-linflexd"; 175 reg = <0x42180000 0x1000>; 176 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 177 status = "disabled"; 178 }; 179 180 uart8: uart@42190000 { 181 compatible = "nxp,s32-linflexd"; 182 reg = <0x42190000 0x1000>; 183 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 184 status = "disabled"; 185 }; 186 187 uart9: uart@42980000 { 188 compatible = "nxp,s32-linflexd"; 189 reg = <0x42980000 0x1000>; 190 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 191 status = "disabled"; 192 }; 193 194 uart10: uart@42990000 { 195 compatible = "nxp,s32-linflexd"; 196 reg = <0x42990000 0x1000>; 197 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 198 status = "disabled"; 199 }; 200 201 uart11: uart@429a0000 { 202 compatible = "nxp,s32-linflexd"; 203 reg = <0x429a0000 0x1000>; 204 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 205 status = "disabled"; 206 }; 207 208 uart12: uart@40330000 { 209 compatible = "nxp,s32-linflexd"; 210 reg = <0x40330000 0x1000>; 211 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 212 status = "disabled"; 213 }; 214 215 siul2_0: siul2@40520000 { 216 reg = <0x40520000 0x10000>; 217 #address-cells = <1>; 218 #size-cells = <1>; 219 220 eirq0: eirq0@40520010 { 221 compatible = "nxp,s32-siul2-eirq"; 222 reg = <0x40520010 0xb4>; 223 #address-cells = <0>; 224 interrupts = <GIC_SPI 514 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 225 interrupt-controller; 226 #interrupt-cells = <2>; 227 status = "disabled"; 228 }; 229 230 gpioa: gpio@40521702 { 231 compatible = "nxp,s32-gpio"; 232 reg = <0x40521702 0x02>, <0x40520240 0x40>; 233 reg-names = "pgpdo", "mscr"; 234 interrupt-parent = <&eirq0>; 235 interrupts = <1 1>, <3 0>, <5 2>, <12 3>, 236 <13 4>, <14 5>, <15 6>; 237 gpio-controller; 238 #gpio-cells = <2>; 239 ngpios = <16>; 240 status = "disabled"; 241 }; 242 243 gpiob: gpio@40521700 { 244 compatible = "nxp,s32-gpio"; 245 reg = <0x40521700 0x02>, <0x40520280 0x40>; 246 reg-names = "pgpdo", "mscr"; 247 interrupt-parent = <&eirq0>; 248 interrupts = <0 7>; 249 gpio-controller; 250 #gpio-cells = <2>; 251 ngpios = <15>; 252 status = "disabled"; 253 }; 254 255 gpioo: gpio@40521716 { 256 compatible = "nxp,s32-gpio"; 257 reg = <0x40521716 0x02>, <0x405204c0 0x40>; 258 reg-names = "pgpdo", "mscr"; 259 gpio-controller; 260 #gpio-cells = <2>; 261 ngpios = <14>; 262 gpio-reserved-ranges = <0 10>; 263 status = "disabled"; 264 }; 265 }; 266 267 siul2_1: siul2@40d20000 { 268 reg = <0x40d20000 0x10000>; 269 #address-cells = <1>; 270 #size-cells = <1>; 271 272 eirq1: eirq1@40d20010 { 273 compatible = "nxp,s32-siul2-eirq"; 274 reg = <0x40d20010 0xb4>; 275 #address-cells = <0>; 276 interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 277 interrupt-controller; 278 #interrupt-cells = <2>; 279 status = "disabled"; 280 }; 281 282 gpioc: gpio@40d21700 { 283 compatible = "nxp,s32-gpio"; 284 reg = <0x40d21700 0x02>, <0x40d20280 0x40>; 285 reg-names = "pgpdo", "mscr"; 286 interrupt-parent = <&eirq1>; 287 interrupts = <3 0>, <5 1>; 288 gpio-controller; 289 #gpio-cells = <2>; 290 ngpios = <16>; 291 gpio-reserved-ranges = <0 15>; 292 status = "disabled"; 293 }; 294 295 gpiod: gpio@40d21706 { 296 compatible = "nxp,s32-gpio"; 297 reg = <0x40d21706 0x02>, <0x40d202c0 0x40>; 298 reg-names = "pgpdo", "mscr"; 299 gpio-controller; 300 #gpio-cells = <2>; 301 ngpios = <16>; 302 status = "disabled"; 303 }; 304 305 gpioe: gpio@40d21704 { 306 compatible = "nxp,s32-gpio"; 307 reg = <0x40d21704 0x02>, <0x40d20300 0x40>; 308 reg-names = "pgpdo", "mscr"; 309 gpio-controller; 310 #gpio-cells = <2>; 311 ngpios = <16>; 312 status = "disabled"; 313 }; 314 315 gpiof: gpio@40d2170a { 316 compatible = "nxp,s32-gpio"; 317 reg = <0x40d2170a 0x02>, <0x40d20340 0x40>; 318 reg-names = "pgpdo", "mscr"; 319 gpio-controller; 320 #gpio-cells = <2>; 321 ngpios = <16>; 322 status = "disabled"; 323 }; 324 325 gpiog: gpio@40d21708 { 326 compatible = "nxp,s32-gpio"; 327 reg = <0x40d21708 0x02>, <0x40d20380 0x40>; 328 reg-names = "pgpdo", "mscr"; 329 interrupt-parent = <&eirq1>; 330 interrupts = <0 2>, <1 3>, <4 4>, 331 <5 5>, <10 6>, <11 7>; 332 gpio-controller; 333 #gpio-cells = <2>; 334 ngpios = <12>; 335 status = "disabled"; 336 }; 337 }; 338 339 siul2_3: siul2@41d20000 { 340 reg = <0x41d20000 0x10000>; 341 }; 342 343 siul2_4: siul2@42520000 { 344 reg = <0x42520000 0x10000>; 345 #address-cells = <1>; 346 #size-cells = <1>; 347 348 eirq4: eirq4@42520010 { 349 compatible = "nxp,s32-siul2-eirq"; 350 reg = <0x42520010 0xb4>; 351 #address-cells = <0>; 352 interrupts = <GIC_SPI 516 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 353 interrupt-controller; 354 #interrupt-cells = <2>; 355 status = "disabled"; 356 }; 357 358 gpioh: gpio@42521708 { 359 compatible = "nxp,s32-gpio"; 360 reg = <0x42521708 0x02>, <0x42520380 0x40>; 361 reg-names = "pgpdo", "mscr"; 362 gpio-controller; 363 #gpio-cells = <2>; 364 ngpios = <16>; 365 gpio-reserved-ranges = <0 12>; 366 status = "disabled"; 367 }; 368 369 gpioi: gpio@4252170e { 370 compatible = "nxp,s32-gpio"; 371 reg = <0x4252170e 0x02>, <0x425203c0 0x40>; 372 reg-names = "pgpdo", "mscr"; 373 interrupt-parent = <&eirq4>; 374 interrupts = <11 0>, <13 1>; 375 gpio-controller; 376 #gpio-cells = <2>; 377 ngpios = <16>; 378 status = "disabled"; 379 }; 380 381 gpioj: gpio@4252170c { 382 compatible = "nxp,s32-gpio"; 383 reg = <0x4252170c 0x02>, <0x42520400 0x40>; 384 reg-names = "pgpdo", "mscr"; 385 interrupt-parent = <&eirq4>; 386 interrupts = <12 2>; 387 gpio-controller; 388 #gpio-cells = <2>; 389 ngpios = <16>; 390 status = "disabled"; 391 }; 392 393 gpiok: gpio@42521712 { 394 compatible = "nxp,s32-gpio"; 395 reg = <0x42521712 0x02>, <0x42520440 0x40>; 396 reg-names = "pgpdo", "mscr"; 397 interrupt-parent = <&eirq4>; 398 interrupts = <4 3>, <6 4>, <9 5>, 399 <11 6>, <13 7>; 400 gpio-controller; 401 #gpio-cells = <2>; 402 ngpios = <16>; 403 status = "disabled"; 404 }; 405 406 gpiol: gpio@42521710 { 407 compatible = "nxp,s32-gpio"; 408 reg = <0x42521710 0x02>, <0x42520480 0x40>; 409 reg-names = "pgpdo", "mscr"; 410 gpio-controller; 411 #gpio-cells = <2>; 412 ngpios = <2>; 413 status = "disabled"; 414 }; 415 }; 416 417 siul2_5: siul2@42d20000 { 418 reg = <0x42d20000 0x10000>; 419 #address-cells = <1>; 420 #size-cells = <1>; 421 422 eirq5: eirq5@42d20010 { 423 compatible = "nxp,s32-siul2-eirq"; 424 reg = <0x42d20010 0xb4>; 425 #address-cells = <0>; 426 interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 427 interrupt-controller; 428 #interrupt-cells = <2>; 429 status = "disabled"; 430 }; 431 432 gpiom: gpio@42d21710 { 433 compatible = "nxp,s32-gpio"; 434 reg = <0x42d21710 0x02>, <0x42d20480 0x40>; 435 reg-names = "pgpdo", "mscr"; 436 interrupt-parent = <&eirq5>; 437 interrupts = <1 0>, <3 1>, <5 2>, <7 3>; 438 gpio-controller; 439 #gpio-cells = <2>; 440 ngpios = <16>; 441 gpio-reserved-ranges = <0 2>; 442 status = "disabled"; 443 }; 444 445 gpion: gpio@42d21716 { 446 compatible = "nxp,s32-gpio"; 447 reg = <0x42d21716 0x02>, <0x42d204c0 0x40>; 448 reg-names = "pgpdo", "mscr"; 449 interrupt-parent = <&eirq5>; 450 interrupts = <0 4>, <2 5>, <5 6>, <6 7>; 451 gpio-controller; 452 #gpio-cells = <2>; 453 ngpios = <10>; 454 status = "disabled"; 455 }; 456 }; 457 458 spi0: spi@40130000 { 459 compatible = "nxp,s32-spi"; 460 reg = <0x40130000 0x10000>; 461 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 462 clocks = <&clock NXP_S32_SPI0_CLK>; 463 num-cs = <5>; 464 #address-cells = <1>; 465 #size-cells = <0>; 466 status = "disabled"; 467 }; 468 469 spi1: spi@40140000 { 470 compatible = "nxp,s32-spi"; 471 reg = <0x40140000 0x10000>; 472 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 473 clocks = <&clock NXP_S32_SPI1_CLK>; 474 num-cs = <5>; 475 #address-cells = <1>; 476 #size-cells = <0>; 477 status = "disabled"; 478 }; 479 480 spi2: spi@40930000 { 481 compatible = "nxp,s32-spi"; 482 reg = <0x40930000 0x10000>; 483 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 484 clocks = <&clock NXP_S32_SPI2_CLK>; 485 num-cs = <5>; 486 #address-cells = <1>; 487 #size-cells = <0>; 488 status = "disabled"; 489 }; 490 491 spi3: spi@40940000 { 492 compatible = "nxp,s32-spi"; 493 reg = <0x40940000 0x10000>; 494 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 495 clocks = <&clock NXP_S32_SPI3_CLK>; 496 num-cs = <5>; 497 #address-cells = <1>; 498 #size-cells = <0>; 499 status = "disabled"; 500 }; 501 502 spi4: spi@40950000 { 503 compatible = "nxp,s32-spi"; 504 reg = <0x40950000 0x10000>; 505 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 506 clocks = <&clock NXP_S32_SPI4_CLK>; 507 num-cs = <5>; 508 #address-cells = <1>; 509 #size-cells = <0>; 510 status = "disabled"; 511 }; 512 513 spi5: spi@42130000 { 514 compatible = "nxp,s32-spi"; 515 reg = <0x42130000 0x10000>; 516 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 517 clocks = <&clock NXP_S32_SPI5_CLK>; 518 num-cs = <5>; 519 #address-cells = <1>; 520 #size-cells = <0>; 521 status = "disabled"; 522 }; 523 524 spi6: spi@42140000 { 525 compatible = "nxp,s32-spi"; 526 reg = <0x42140000 0x10000>; 527 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 528 clocks = <&clock NXP_S32_SPI6_CLK>; 529 num-cs = <5>; 530 #address-cells = <1>; 531 #size-cells = <0>; 532 status = "disabled"; 533 }; 534 535 spi7: spi@42150000 { 536 compatible = "nxp,s32-spi"; 537 reg = <0x42150000 0x10000>; 538 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 539 clocks = <&clock NXP_S32_SPI7_CLK>; 540 num-cs = <5>; 541 #address-cells = <1>; 542 #size-cells = <0>; 543 status = "disabled"; 544 }; 545 546 spi8: spi@42930000 { 547 compatible = "nxp,s32-spi"; 548 reg = <0x42930000 0x10000>; 549 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 550 clocks = <&clock NXP_S32_SPI8_CLK>; 551 num-cs = <5>; 552 #address-cells = <1>; 553 #size-cells = <0>; 554 status = "disabled"; 555 }; 556 557 spi9: spi@42940000 { 558 compatible = "nxp,s32-spi"; 559 reg = <0x42940000 0x10000>; 560 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 561 clocks = <&clock NXP_S32_SPI9_CLK>; 562 num-cs = <5>; 563 #address-cells = <1>; 564 #size-cells = <0>; 565 status = "disabled"; 566 }; 567 568 dspi0: spi@40340000 { 569 compatible = "nxp,dspi"; 570 reg = <0x40340000 0x10000>; 571 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 572 clocks = <&clock NXP_S32_MSCDSPI_CLK>; 573 #address-cells = <1>; 574 #size-cells = <0>; 575 status = "disabled"; 576 }; 577 578 mru0: mbox@76070000 { 579 compatible = "nxp,s32-mru"; 580 reg = <0x76070000 0x10000>; 581 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 582 #mbox-cells = <1>; 583 status = "disabled"; 584 }; 585 586 mru1: mbox@76090000 { 587 compatible = "nxp,s32-mru"; 588 reg = <0x76090000 0x10000>; 589 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 590 #mbox-cells = <1>; 591 status = "disabled"; 592 }; 593 594 mru2: mbox@76270000 { 595 compatible = "nxp,s32-mru"; 596 reg = <0x76270000 0x10000>; 597 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 598 #mbox-cells = <1>; 599 status = "disabled"; 600 }; 601 602 mru3: mbox@76290000 { 603 compatible = "nxp,s32-mru"; 604 reg = <0x76290000 0x10000>; 605 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 606 #mbox-cells = <1>; 607 status = "disabled"; 608 }; 609 610 mru4: mbox@76870000 { 611 compatible = "nxp,s32-mru"; 612 reg = <0x76870000 0x10000>; 613 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 614 #mbox-cells = <1>; 615 status = "disabled"; 616 }; 617 618 mru5: mbox@76890000 { 619 compatible = "nxp,s32-mru"; 620 reg = <0x76890000 0x10000>; 621 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 622 #mbox-cells = <1>; 623 status = "disabled"; 624 }; 625 626 mru6: mbox@76a70000 { 627 compatible = "nxp,s32-mru"; 628 reg = <0x76a70000 0x10000>; 629 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 630 #mbox-cells = <1>; 631 status = "disabled"; 632 }; 633 634 mru7: mbox@76a90000 { 635 compatible = "nxp,s32-mru"; 636 reg = <0x76a90000 0x10000>; 637 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 638 #mbox-cells = <1>; 639 status = "disabled"; 640 }; 641 642 netc: ethernet@74000000 { 643 reg = <0x74000000 0x1000000>; 644 #address-cells = <1>; 645 #size-cells = <1>; 646 ranges; 647 648 emdio: mdio@74b60000 { 649 compatible = "nxp,s32-netc-emdio"; 650 reg = <0x74b60000 0x1c44>; 651 status = "disabled"; 652 #address-cells = <1>; 653 #size-cells = <0>; 654 }; 655 656 enetc_psi0: ethernet@74b00000 { 657 compatible = "nxp,s32-netc-psi"; 658 reg = <0x74b00000 0x10000>; 659 status = "disabled"; 660 }; 661 662 enetc_vsi1: ethernet@74bc0000 { 663 compatible = "nxp,s32-netc-vsi"; 664 reg = <0x74bc0000 0x10000>; 665 status = "disabled"; 666 }; 667 668 enetc_vsi2: ethernet@74bd0000 { 669 compatible = "nxp,s32-netc-vsi"; 670 reg = <0x74bd0000 0x10000>; 671 status = "disabled"; 672 }; 673 674 enetc_vsi3: ethernet@74be0000 { 675 compatible = "nxp,s32-netc-vsi"; 676 reg = <0x74be0000 0x10000>; 677 status = "disabled"; 678 }; 679 680 enetc_vsi4: ethernet@74bf0000 { 681 compatible = "nxp,s32-netc-vsi"; 682 reg = <0x74bf0000 0x10000>; 683 status = "disabled"; 684 }; 685 686 enetc_vsi5: ethernet@74c00000 { 687 compatible = "nxp,s32-netc-vsi"; 688 reg = <0x74c00000 0x10000>; 689 status = "disabled"; 690 }; 691 692 enetc_vsi6: ethernet@74c10000 { 693 compatible = "nxp,s32-netc-vsi"; 694 reg = <0x74c10000 0x10000>; 695 status = "disabled"; 696 }; 697 698 enetc_vsi7: ethernet@74c20000 { 699 compatible = "nxp,s32-netc-vsi"; 700 reg = <0x74c20000 0x10000>; 701 status = "disabled"; 702 }; 703 }; 704 705 canxl0: can@4741b000 { 706 compatible = "nxp,s32-canxl"; 707 reg = <0x4741b000 0x1000>, 708 <0x47423000 0x1000>, 709 <0x47425000 0x1000>, 710 <0x47427000 0x1000>; 711 reg-names = "sic", "rx_fifo", "rx_fifo_ctrl", "mru"; 712 status = "disabled"; 713 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 714 <GIC_SPI 225 IRQ_TYPE_LEVEL 0xb0>; 715 interrupt-names = "rx_tx_mru", "error"; 716 clocks = <&clock NXP_S32_P5_CANXL_PE_CLK>; 717 }; 718 719 canxl1: can@4751b000 { 720 compatible = "nxp,s32-canxl"; 721 reg = <0x4751b000 0x1000>, 722 <0x47523000 0x1000>, 723 <0x47525000 0x1000>, 724 <0x47527000 0x1000>; 725 reg-names = "sic", "rx_fifo", "rx_fifo_ctrl", "mru"; 726 status = "disabled"; 727 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 728 <GIC_SPI 227 IRQ_TYPE_LEVEL 0xb0>; 729 interrupt-names = "rx_tx_mru", "error"; 730 clocks = <&clock NXP_S32_P5_CANXL_PE_CLK>; 731 }; 732 733 flexcan0: can@449a0000 { 734 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 735 reg = <0x449a0000 0x4000>; 736 clk-source = <0>; 737 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 738 <GIC_SPI 583 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 739 <GIC_SPI 584 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 740 <GIC_SPI 585 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 741 <GIC_SPI 586 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 742 interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", 743 "ored_64_95_mb", "ored_96_127_mb"; 744 clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; 745 status = "disabled"; 746 }; 747 748 flexcan1: can@449b0000 { 749 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 750 reg = <0x449b0000 0x4000>; 751 clk-source = <0>; 752 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 753 <GIC_SPI 589 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 754 <GIC_SPI 590 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 755 <GIC_SPI 591 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 756 <GIC_SPI 592 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 757 interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", 758 "ored_64_95_mb", "ored_96_127_mb"; 759 clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; 760 status = "disabled"; 761 }; 762 763 flexcan2: can@449c0000 { 764 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 765 clk-source = <0>; 766 reg = <0x449c0000 0x4000>; 767 interrupts = <GIC_SPI 593 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 768 <GIC_SPI 595 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 769 <GIC_SPI 596 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 770 <GIC_SPI 597 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 771 <GIC_SPI 598 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 772 interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", 773 "ored_64_95_mb", "ored_96_127_mb"; 774 clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; 775 status = "disabled"; 776 }; 777 778 flexcan3: can@449d0000 { 779 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 780 clk-source = <0>; 781 reg = <0x449d0000 0x4000>; 782 interrupts = <GIC_SPI 599 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 783 <GIC_SPI 601 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 784 <GIC_SPI 602 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 785 <GIC_SPI 603 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 786 <GIC_SPI 604 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 787 interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", 788 "ored_64_95_mb", "ored_96_127_mb"; 789 clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; 790 status = "disabled"; 791 }; 792 793 flexcan4: can@449e0000 { 794 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 795 clk-source = <0>; 796 reg = <0x449e0000 0x4000>; 797 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 798 <GIC_SPI 607 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 799 <GIC_SPI 608 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 800 <GIC_SPI 609 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 801 <GIC_SPI 610 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 802 interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", 803 "ored_64_95_mb", "ored_96_127_mb"; 804 clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; 805 status = "disabled"; 806 }; 807 808 flexcan5: can@449f0000 { 809 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 810 clk-source = <0>; 811 reg = <0x449f0000 0x4000>; 812 interrupts = <GIC_SPI 611 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 813 <GIC_SPI 613 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 814 <GIC_SPI 614 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 815 <GIC_SPI 615 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 816 <GIC_SPI 616 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 817 interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", 818 "ored_64_95_mb", "ored_96_127_mb"; 819 clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; 820 status = "disabled"; 821 }; 822 823 flexcan6: can@44ba0000 { 824 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 825 clk-source = <0>; 826 reg = <0x44ba0000 0x4000>; 827 interrupts = <GIC_SPI 617 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 828 <GIC_SPI 619 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 829 <GIC_SPI 620 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 830 <GIC_SPI 621 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 831 <GIC_SPI 622 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 832 interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", 833 "ored_64_95_mb", "ored_96_127_mb"; 834 clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; 835 status = "disabled"; 836 }; 837 838 flexcan7: can@44bb0000 { 839 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 840 clk-source = <0>; 841 reg = <0x44bb0000 0x4000>; 842 interrupts = <GIC_SPI 623 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 843 <GIC_SPI 625 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 844 <GIC_SPI 626 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 845 <GIC_SPI 627 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 846 <GIC_SPI 628 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 847 interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", 848 "ored_64_95_mb", "ored_96_127_mb"; 849 clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; 850 status = "disabled"; 851 }; 852 853 flexcan8: can@44bc0000 { 854 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 855 clk-source = <0>; 856 reg = <0x44bc0000 0x4000>; 857 interrupts = <GIC_SPI 629 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 858 <GIC_SPI 631 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 859 <GIC_SPI 632 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 860 <GIC_SPI 633 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 861 <GIC_SPI 634 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 862 interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", 863 "ored_64_95_mb", "ored_96_127_mb"; 864 clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; 865 status = "disabled"; 866 }; 867 868 flexcan9: can@44bd0000 { 869 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 870 clk-source = <0>; 871 reg = <0x44bd0000 0x4000>; 872 interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 873 <GIC_SPI 637 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 874 <GIC_SPI 638 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 875 <GIC_SPI 639 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 876 <GIC_SPI 640 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 877 interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", 878 "ored_64_95_mb", "ored_96_127_mb"; 879 clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; 880 status = "disabled"; 881 }; 882 883 flexcan10: can@44be0000 { 884 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 885 clk-source = <0>; 886 reg = <0x44be0000 0x4000>; 887 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 888 <GIC_SPI 643 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 889 <GIC_SPI 644 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 890 <GIC_SPI 645 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 891 <GIC_SPI 646 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 892 interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", 893 "ored_64_95_mb", "ored_96_127_mb"; 894 clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; 895 status = "disabled"; 896 }; 897 898 flexcan11: can@44bf0000 { 899 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 900 clk-source = <0>; 901 reg = <0x44bf0000 0x4000>; 902 interrupts = <GIC_SPI 647 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 903 <GIC_SPI 649 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 904 <GIC_SPI 650 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 905 <GIC_SPI 651 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 906 <GIC_SPI 652 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 907 interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", 908 "ored_64_95_mb", "ored_96_127_mb"; 909 clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; 910 status = "disabled"; 911 }; 912 913 flexcan12: can@44da0000 { 914 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 915 clk-source = <0>; 916 reg = <0x44da0000 0x4000>; 917 interrupts = <GIC_SPI 653 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 918 <GIC_SPI 655 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 919 <GIC_SPI 656 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 920 <GIC_SPI 657 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 921 <GIC_SPI 658 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 922 interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", 923 "ored_64_95_mb", "ored_96_127_mb"; 924 clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; 925 status = "disabled"; 926 }; 927 928 flexcan13: can@44db0000 { 929 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 930 clk-source = <0>; 931 reg = <0x44db0000 0x4000>; 932 interrupts = <GIC_SPI 659 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 933 <GIC_SPI 661 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 934 <GIC_SPI 662 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 935 <GIC_SPI 663 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 936 <GIC_SPI 664 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 937 interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", 938 "ored_64_95_mb", "ored_96_127_mb"; 939 clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; 940 status = "disabled"; 941 }; 942 943 flexcan14: can@44dc0000 { 944 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 945 clk-source = <0>; 946 reg = <0x44dc0000 0x4000>; 947 interrupts = <GIC_SPI 665 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 948 <GIC_SPI 667 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 949 <GIC_SPI 668 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 950 <GIC_SPI 669 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 951 <GIC_SPI 670 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 952 interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", 953 "ored_64_95_mb", "ored_96_127_mb"; 954 clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; 955 status = "disabled"; 956 }; 957 958 flexcan15: can@44dd0000 { 959 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 960 clk-source = <0>; 961 reg = <0x44dd0000 0x4000>; 962 interrupts = <GIC_SPI 671 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 963 <GIC_SPI 673 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 964 <GIC_SPI 674 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 965 <GIC_SPI 675 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 966 <GIC_SPI 676 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 967 interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", 968 "ored_64_95_mb", "ored_96_127_mb"; 969 clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; 970 status = "disabled"; 971 }; 972 973 flexcan16: can@44de0000 { 974 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 975 clk-source = <0>; 976 reg = <0x44de0000 0x4000>; 977 interrupts = <GIC_SPI 677 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 978 <GIC_SPI 679 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 979 <GIC_SPI 680 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 980 <GIC_SPI 681 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 981 <GIC_SPI 682 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 982 interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", 983 "ored_64_95_mb", "ored_96_127_mb"; 984 clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; 985 status = "disabled"; 986 }; 987 988 flexcan17: can@44df0000 { 989 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 990 clk-source = <0>; 991 reg = <0x44df0000 0x4000>; 992 interrupts = <GIC_SPI 683 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 993 <GIC_SPI 685 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 994 <GIC_SPI 686 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 995 <GIC_SPI 687 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 996 <GIC_SPI 688 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 997 interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", 998 "ored_64_95_mb", "ored_96_127_mb"; 999 clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; 1000 status = "disabled"; 1001 }; 1002 1003 flexcan18: can@44fa0000 { 1004 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 1005 clk-source = <0>; 1006 reg = <0x44fa0000 0x4000>; 1007 interrupts = <GIC_SPI 689 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1008 <GIC_SPI 691 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1009 <GIC_SPI 692 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1010 <GIC_SPI 693 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1011 <GIC_SPI 694 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 1012 interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", 1013 "ored_64_95_mb", "ored_96_127_mb"; 1014 clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; 1015 status = "disabled"; 1016 }; 1017 1018 flexcan19: can@44fb0000 { 1019 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 1020 clk-source = <0>; 1021 reg = <0x44fb0000 0x4000>; 1022 interrupts = <GIC_SPI 695 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1023 <GIC_SPI 697 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1024 <GIC_SPI 698 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1025 <GIC_SPI 699 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1026 <GIC_SPI 700 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 1027 interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", 1028 "ored_64_95_mb", "ored_96_127_mb"; 1029 clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; 1030 status = "disabled"; 1031 }; 1032 1033 flexcan20: can@44fc0000 { 1034 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 1035 clk-source = <0>; 1036 reg = <0x44fc0000 0x4000>; 1037 interrupts = <GIC_SPI 701 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1038 <GIC_SPI 703 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1039 <GIC_SPI 704 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1040 <GIC_SPI 705 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1041 <GIC_SPI 706 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 1042 interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", 1043 "ored_64_95_mb", "ored_96_127_mb"; 1044 clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; 1045 status = "disabled"; 1046 }; 1047 1048 flexcan21: can@44fd0000 { 1049 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 1050 clk-source = <0>; 1051 reg = <0x44fd0000 0x4000>; 1052 interrupts = <GIC_SPI 707 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1053 <GIC_SPI 709 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1054 <GIC_SPI 710 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1055 <GIC_SPI 711 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1056 <GIC_SPI 712 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 1057 interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", 1058 "ored_64_95_mb", "ored_96_127_mb"; 1059 clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; 1060 status = "disabled"; 1061 }; 1062 1063 flexcan22: can@44fe0000 { 1064 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 1065 clk-source = <0>; 1066 reg = <0x44fe0000 0x4000>; 1067 interrupts = <GIC_SPI 713 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1068 <GIC_SPI 715 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1069 <GIC_SPI 716 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1070 <GIC_SPI 717 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1071 <GIC_SPI 718 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 1072 interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", 1073 "ored_64_95_mb", "ored_96_127_mb"; 1074 clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; 1075 status = "disabled"; 1076 }; 1077 1078 flexcan23: can@44ff0000 { 1079 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 1080 clk-source = <0>; 1081 reg = <0x44ff0000 0x4000>; 1082 interrupts = <GIC_SPI 719 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1083 <GIC_SPI 721 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1084 <GIC_SPI 722 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1085 <GIC_SPI 723 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1086 <GIC_SPI 724 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 1087 interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", 1088 "ored_64_95_mb", "ored_96_127_mb"; 1089 clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; 1090 status = "disabled"; 1091 }; 1092 1093 sar_adc0: adc@402c0000 { 1094 compatible = "nxp,s32-adc-sar"; 1095 reg = <0x402C0000 0x1000>; 1096 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1097 <GIC_SPI 169 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1098 <GIC_SPI 170 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 1099 #io-channel-cells = <1>; 1100 status = "disabled"; 1101 }; 1102 1103 sar_adc1: adc@402e0000 { 1104 compatible = "nxp,s32-adc-sar"; 1105 reg = <0x402e0000 0x1000>; 1106 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1107 <GIC_SPI 202 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1108 <GIC_SPI 203 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 1109 #io-channel-cells = <1>; 1110 status = "disabled"; 1111 }; 1112 1113 lpi2c1: i2c@409d0000 { 1114 compatible = "nxp,lpi2c"; 1115 reg = <0x409d0000 0x10000>; 1116 #address-cells = <1>; 1117 #size-cells = <0>; 1118 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 1119 clocks = <&clock NXP_S32_P1_REG_INTF_CLK>; 1120 clock-frequency = <I2C_BITRATE_STANDARD>; 1121 status = "disabled"; 1122 }; 1123 1124 lpi2c2: i2c@421d0000 { 1125 compatible = "nxp,lpi2c"; 1126 reg = <0x421d0000 0x10000>; 1127 #address-cells = <1>; 1128 #size-cells = <0>; 1129 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 1130 clocks = <&clock NXP_S32_P4_REG_INTF_CLK>; 1131 clock-frequency = <I2C_BITRATE_STANDARD>; 1132 status = "disabled"; 1133 }; 1134 1135 edma0: dma-controller@405d0000 { 1136 compatible = "nxp,mcux-edma"; 1137 nxp,version = <3>; 1138 reg = <0x405d0000 0x10000>, <0x405a0000 0x10000>, <0x405b0000 0x100000>; 1139 dma-channels = <32>; 1140 dma-requests = <64>; 1141 dmamux-reg-offset = <3>; 1142 #dma-cells = <2>; 1143 nxp,mem2mem; 1144 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1145 <GIC_SPI 32 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1146 <GIC_SPI 33 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1147 <GIC_SPI 34 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1148 <GIC_SPI 35 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1149 <GIC_SPI 36 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1150 <GIC_SPI 37 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1151 <GIC_SPI 38 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1152 <GIC_SPI 39 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1153 <GIC_SPI 40 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1154 <GIC_SPI 41 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1155 <GIC_SPI 42 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1156 <GIC_SPI 43 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1157 <GIC_SPI 44 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1158 <GIC_SPI 45 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1159 <GIC_SPI 46 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1160 <GIC_SPI 47 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1161 <GIC_SPI 48 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1162 <GIC_SPI 49 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1163 <GIC_SPI 50 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1164 <GIC_SPI 51 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1165 <GIC_SPI 52 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1166 <GIC_SPI 53 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1167 <GIC_SPI 54 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1168 <GIC_SPI 55 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1169 <GIC_SPI 56 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1170 <GIC_SPI 57 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1171 <GIC_SPI 58 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1172 <GIC_SPI 59 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1173 <GIC_SPI 60 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1174 <GIC_SPI 61 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1175 <GIC_SPI 62 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1176 <GIC_SPI 28 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 1177 status = "disabled"; 1178 }; 1179 1180 edma1: dma-controller@40dd0000 { 1181 compatible = "nxp,mcux-edma"; 1182 nxp,version = <3>; 1183 reg = <0x40dd0000 0x10000>, <0x40da0000 0x10000>; 1184 dma-channels = <16>; 1185 dma-requests = <64>; 1186 dmamux-reg-offset = <3>; 1187 #dma-cells = <2>; 1188 nxp,mem2mem; 1189 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1190 <GIC_SPI 66 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1191 <GIC_SPI 67 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1192 <GIC_SPI 68 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1193 <GIC_SPI 69 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1194 <GIC_SPI 70 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1195 <GIC_SPI 71 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1196 <GIC_SPI 72 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1197 <GIC_SPI 73 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1198 <GIC_SPI 74 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1199 <GIC_SPI 75 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1200 <GIC_SPI 76 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1201 <GIC_SPI 77 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1202 <GIC_SPI 78 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1203 <GIC_SPI 79 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1204 <GIC_SPI 80 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1205 <GIC_SPI 63 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 1206 status = "disabled"; 1207 }; 1208 1209 edma4: dma-controller@425d0000 { 1210 compatible = "nxp,mcux-edma"; 1211 nxp,version = <3>; 1212 reg = <0x425d0000 0x10000>, <0x425a0000 0x10000>; 1213 dma-channels = <32>; 1214 dma-requests = <64>; 1215 dmamux-reg-offset = <3>; 1216 #dma-cells = <2>; 1217 nxp,mem2mem; 1218 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1219 <GIC_SPI 84 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1220 <GIC_SPI 85 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1221 <GIC_SPI 86 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1222 <GIC_SPI 87 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1223 <GIC_SPI 88 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1224 <GIC_SPI 89 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1225 <GIC_SPI 90 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1226 <GIC_SPI 91 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1227 <GIC_SPI 92 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1228 <GIC_SPI 93 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1229 <GIC_SPI 94 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1230 <GIC_SPI 95 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1231 <GIC_SPI 96 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1232 <GIC_SPI 97 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1233 <GIC_SPI 98 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1234 <GIC_SPI 81 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 1235 status = "disabled"; 1236 }; 1237 1238 edma5: dma-controller@42dd0000 { 1239 compatible = "nxp,mcux-edma"; 1240 nxp,version = <3>; 1241 reg = <0x42dd0000 0x10000>, <0x42da0000 0x10000>; 1242 dma-channels = <32>; 1243 dma-requests = <64>; 1244 dmamux-reg-offset = <3>; 1245 #dma-cells = <2>; 1246 nxp,mem2mem; 1247 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1248 <GIC_SPI 102 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1249 <GIC_SPI 103 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1250 <GIC_SPI 104 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1251 <GIC_SPI 105 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1252 <GIC_SPI 106 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1253 <GIC_SPI 107 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1254 <GIC_SPI 108 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1255 <GIC_SPI 109 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1256 <GIC_SPI 110 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1257 <GIC_SPI 111 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1258 <GIC_SPI 112 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1259 <GIC_SPI 113 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1260 <GIC_SPI 114 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1261 <GIC_SPI 115 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1262 <GIC_SPI 116 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1263 <GIC_SPI 99 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 1264 status = "disabled"; 1265 }; 1266 1267 emios0: emios@420b0000 { 1268 compatible = "nxp,s32-emios"; 1269 reg = <0x420b0000 0x4000>; 1270 clocks = <&clock NXP_S32_P4_REG_INTF_CLK>; 1271 internal-cnt = <0xFFFFFFFF>; 1272 interrupts = <GIC_SPI 284 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1273 <GIC_SPI 285 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1274 <GIC_SPI 286 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1275 <GIC_SPI 287 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1276 <GIC_SPI 288 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1277 <GIC_SPI 289 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1278 <GIC_SPI 290 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1279 <GIC_SPI 291 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1280 <GIC_SPI 292 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1281 <GIC_SPI 293 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1282 <GIC_SPI 294 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1283 <GIC_SPI 295 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1284 <GIC_SPI 296 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1285 <GIC_SPI 297 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1286 <GIC_SPI 298 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1287 <GIC_SPI 299 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1288 <GIC_SPI 300 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1289 <GIC_SPI 301 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1290 <GIC_SPI 302 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1291 <GIC_SPI 303 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1292 <GIC_SPI 304 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1293 <GIC_SPI 305 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1294 <GIC_SPI 306 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1295 <GIC_SPI 307 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1296 <GIC_SPI 308 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1297 <GIC_SPI 309 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1298 <GIC_SPI 310 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1299 <GIC_SPI 311 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1300 <GIC_SPI 312 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 1301 interrupt-names = "0_CH0", "0_CH1", "0_CH2", "0_CH3", "0_CH4", 1302 "0_CH5", "0_CH6", "0_CH7", "0_CH8", "0_CH9", 1303 "0_CH10", "0_CH12", "0_CH14", "0_CH16", 1304 "0_CH17", "0_CH18", "0_CH19", "0_CH20", 1305 "0_CH21", "0_CH22", "0_CH23", "0_CH24", 1306 "0_CH25", "0_CH26", "0_CH27", "0_CH28", 1307 "0_CH29", "0_CH30", "0_CH31"; 1308 status = "disabled"; 1309 1310 master_bus { 1311 emios0_bus_a: emios0_bus_a { 1312 channel = <23>; 1313 bus-type = "BUS_A"; 1314 channel-mask = <0xFF7FFFFF>; 1315 status = "disabled"; 1316 }; 1317 1318 emios0_bus_b: emios0_bus_b { 1319 channel = <0>; 1320 bus-type = "BUS_B"; 1321 channel-mask = <0x000000FE>; 1322 status = "disabled"; 1323 }; 1324 1325 emios0_bus_c: emios0_bus_c { 1326 channel = <8>; 1327 bus-type = "BUS_C"; 1328 channel-mask = <0x0000FE00>; 1329 status = "disabled"; 1330 }; 1331 1332 emios0_bus_d: emios0_bus_d { 1333 channel = <16>; 1334 bus-type = "BUS_D"; 1335 channel-mask = <0x00FE0000>; 1336 status = "disabled"; 1337 }; 1338 1339 emios0_bus_e: emios0_bus_e { 1340 channel = <24>; 1341 bus-type = "BUS_E"; 1342 channel-mask = <0xFE000000>; 1343 status = "disabled"; 1344 }; 1345 }; 1346 1347 pwm { 1348 compatible = "nxp,s32-emios-pwm"; 1349 #pwm-cells = <3>; 1350 status = "disabled"; 1351 }; 1352 }; 1353 1354 emios1: emios@400b0000 { 1355 compatible = "nxp,s32-emios"; 1356 reg = <0x400b0000 0x4000>; 1357 clocks = <&clock NXP_S32_P0_REG_INTF_CLK>; 1358 internal-cnt = <0xFFFFFFFF>; 1359 interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1360 <GIC_SPI 315 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1361 <GIC_SPI 316 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1362 <GIC_SPI 317 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1363 <GIC_SPI 318 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1364 <GIC_SPI 319 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1365 <GIC_SPI 320 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1366 <GIC_SPI 321 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1367 <GIC_SPI 322 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1368 <GIC_SPI 323 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1369 <GIC_SPI 324 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1370 <GIC_SPI 325 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1371 <GIC_SPI 326 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1372 <GIC_SPI 327 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1373 <GIC_SPI 328 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1374 <GIC_SPI 329 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1375 <GIC_SPI 330 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1376 <GIC_SPI 331 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1377 <GIC_SPI 332 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1378 <GIC_SPI 333 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1379 <GIC_SPI 334 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1380 <GIC_SPI 335 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1381 <GIC_SPI 336 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1382 <GIC_SPI 337 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1383 <GIC_SPI 338 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1384 <GIC_SPI 339 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1385 <GIC_SPI 340 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1386 <GIC_SPI 341 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 1387 interrupt-names = "1_CH0", "1_CH1", "1_CH2", "1_CH3", "1_CH4", 1388 "1_CH5", "1_CH6", "1_CH7", "1_CH8", "1_CH10", 1389 "1_CH12", "1_CH14", "1_CH16", "1_CH17", 1390 "1_CH18", "1_CH19", "1_CH20", "1_CH21", 1391 "1_CH22", "1_CH23", "1_CH24", "1_CH25", 1392 "1_CH26", "1_CH27", "1_CH28", "1_CH29", 1393 "1_CH30", "1_CH31"; 1394 status = "disabled"; 1395 1396 master_bus { 1397 emios1_bus_a: emios1_bus_a { 1398 channel = <23>; 1399 bus-type = "BUS_A"; 1400 channel-mask = <0xFF7FFFFF>; 1401 status = "disabled"; 1402 }; 1403 1404 emios1_bus_b: emios1_bus_b { 1405 channel = <0>; 1406 bus-type = "BUS_B"; 1407 channel-mask = <0x000000FE>; 1408 status = "disabled"; 1409 }; 1410 1411 emios1_bus_c: emios1_bus_c { 1412 channel = <8>; 1413 bus-type = "BUS_C"; 1414 channel-mask = <0x0000FE00>; 1415 status = "disabled"; 1416 }; 1417 1418 emios1_bus_d: emios1_bus_d { 1419 channel = <16>; 1420 bus-type = "BUS_D"; 1421 channel-mask = <0x00FE0000>; 1422 status = "disabled"; 1423 }; 1424 1425 emios1_bus_e: emios1_bus_e { 1426 channel = <24>; 1427 channel-mask = <0xFE000000>; 1428 bus-type = "BUS_E"; 1429 status = "disabled"; 1430 }; 1431 }; 1432 1433 pwm { 1434 compatible = "nxp,s32-emios-pwm"; 1435 #pwm-cells = <3>; 1436 status = "disabled"; 1437 }; 1438 }; 1439 1440 qspi0: qspi@42320000 { 1441 compatible = "nxp,s32-qspi"; 1442 reg = <0x42320000 0x4000>; 1443 #address-cells = <1>; 1444 #size-cells = <0>; 1445 status = "disabled"; 1446 }; 1447 1448 qspi1: qspi@42340000 { 1449 compatible = "nxp,s32-qspi"; 1450 reg = <0x42340000 0x4000>; 1451 #address-cells = <1>; 1452 #size-cells = <0>; 1453 status = "disabled"; 1454 }; 1455 }; 1456}; 1457
