1/*
2 * Copyright (c) 2019 Nordic Semiconductor ASA
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm/armv8-m.dtsi>
8#include "nrf_common.dtsi"
9
10/ {
11	cpus {
12		#address-cells = <1>;
13		#size-cells = <0>;
14
15		cpu0: cpu@0 {
16			device_type = "cpu";
17			compatible = "arm,cortex-m33f";
18			reg = <0>;
19			#address-cells = <1>;
20			#size-cells = <1>;
21
22			itm: itm@e0000000 {
23				compatible = "arm,armv8m-itm";
24				reg = <0xe0000000 0x1000>;
25				swo-ref-frequency = <64000000>;
26			};
27
28			mpu: mpu@e000ed90 {
29				compatible = "arm,armv8m-mpu";
30				reg = <0xe000ed90 0x40>;
31			};
32		};
33	};
34
35	chosen {
36		zephyr,entropy = &rng_hci;
37		zephyr,flash-controller = &flash_controller;
38	};
39
40	soc {
41		ficr: ficr@ff0000 {
42			compatible = "nordic,nrf-ficr";
43			reg = <0xff0000 0x1000>;
44			status = "okay";
45		};
46
47		uicr: uicr@ff8000 {
48			compatible = "nordic,nrf-uicr";
49			reg = <0xff8000 0x1000>;
50			status = "okay";
51		};
52
53		sram0: memory@20000000 {
54			compatible = "mmio-sram";
55		};
56
57		peripheral@50000000 {
58			#address-cells = <1>;
59			#size-cells = <1>;
60			ranges = <0x0 0x50000000 0x10000000>;
61
62			/* Common nRF5340 Application MCU
63			 * peripheral description
64			 */
65			#include "nrf5340_cpuapp_peripherals.dtsi"
66		};
67
68		/* Additional Secure peripherals */
69
70		spu: spu@50003000 {
71			compatible = "nordic,nrf-spu";
72			reg = <0x50003000 0x1000>;
73			interrupts = <3 NRF_DEFAULT_IRQ_PRIORITY>;
74			status = "okay";
75		};
76
77		/*
78		 * GPIOTE0 is always accessible as a secure peripheral,
79		 * so we give it the 'gpiote' label for use when building
80		 * code for this target.
81		 */
82		gpiote: gpiote0: gpiote@5000d000 {
83			compatible = "nordic,nrf-gpiote";
84			reg = <0x5000d000 0x1000>;
85			interrupts = <13 5>;
86			status = "disabled";
87		};
88
89		cryptocell: crypto@50844000 {
90			compatible = "nordic,cryptocell", "arm,cryptocell-312";
91			reg = <0x50844000 0x1000>, <0x50845000 0x1000>;
92			reg-names = "wrapper", "core";
93			interrupts = <68 NRF_DEFAULT_IRQ_PRIORITY>;
94			status = "disabled";
95		};
96	};
97
98	/* Default IPC description */
99	ipc {
100		#include "nrf5340_cpuapp_ipc.dtsi"
101	};
102};
103
104&nvic {
105	arm,num-irq-priority-bits = <3>;
106};
107
108/*
109 * Include the non-secure peripherals file here since
110 * it expects to be at the root level. This provides
111 * a node for GPIOTE1.
112 */
113#include "nrf5340_cpuapp_peripherals_ns.dtsi"
114