1/*
2 * Copyright (c) 2022 Teslabs Engineering S.L.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <arm/gd/gd32e50x/gd32e50x.dtsi>
9
10/ {
11	soc {
12		timer7: timer@40013400 {
13			compatible = "gd,gd32-timer";
14			reg = <0x40013400 0x400>;
15			interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
16			interrupt-names = "brk", "up", "trgcom", "cc";
17			clocks = <&cctl GD32_CLOCK_TIMER7>;
18			resets = <&rctl GD32_RESET_TIMER7>;
19			is-advanced;
20			channels = <4>;
21			status = "disabled";
22
23			pwm {
24				compatible = "gd,gd32-pwm";
25				status = "disabled";
26				#pwm-cells = <3>;
27			};
28		};
29
30		timer8: timer@40014c00 {
31			compatible = "gd,gd32-timer";
32			reg = <0x40014c00 0x400>;
33			interrupts = <24 0>;
34			interrupt-names = "global";
35			clocks = <&cctl GD32_CLOCK_TIMER8>;
36			resets = <&rctl GD32_RESET_TIMER8>;
37			channels = <2>;
38			status = "disabled";
39
40			pwm {
41				compatible = "gd,gd32-pwm";
42				status = "disabled";
43				#pwm-cells = <3>;
44			};
45		};
46
47		timer9: timer@40015000 {
48			compatible = "gd,gd32-timer";
49			reg = <0x40015000 0x400>;
50			interrupts = <25 0>;
51			interrupt-names = "global";
52			clocks = <&cctl GD32_CLOCK_TIMER9>;
53			resets = <&rctl GD32_RESET_TIMER9>;
54			channels = <1>;
55			status = "disabled";
56
57			pwm {
58				compatible = "gd,gd32-pwm";
59				status = "disabled";
60				#pwm-cells = <3>;
61			};
62		};
63
64		timer10: timer@40015400 {
65			compatible = "gd,gd32-timer";
66			reg = <0x40015400 0x400>;
67			interrupts = <26 0>;
68			interrupt-names = "global";
69			clocks = <&cctl GD32_CLOCK_TIMER10>;
70			resets = <&rctl GD32_RESET_TIMER10>;
71			channels = <1>;
72			status = "disabled";
73
74			pwm {
75				compatible = "gd,gd32-pwm";
76				status = "disabled";
77				#pwm-cells = <3>;
78			};
79		};
80
81		timer11: timer@40001800 {
82			compatible = "gd,gd32-timer";
83			reg = <0x40001800 0x400>;
84			interrupts = <43 0>;
85			interrupt-names = "global";
86			clocks = <&cctl GD32_CLOCK_TIMER11>;
87			resets = <&rctl GD32_RESET_TIMER11>;
88			channels = <2>;
89			status = "disabled";
90
91			pwm {
92				compatible = "gd,gd32-pwm";
93				status = "disabled";
94				#pwm-cells = <3>;
95			};
96		};
97
98		timer12: timer@40001c00 {
99			compatible = "gd,gd32-timer";
100			reg = <0x40001c00 0x400>;
101			interrupts = <44 0>;
102			interrupt-names = "global";
103			clocks = <&cctl GD32_CLOCK_TIMER12>;
104			resets = <&rctl GD32_RESET_TIMER12>;
105			channels = <1>;
106			status = "disabled";
107
108			pwm {
109				compatible = "gd,gd32-pwm";
110				status = "disabled";
111				#pwm-cells = <3>;
112			};
113		};
114
115		timer13: timer@40002000 {
116			compatible = "gd,gd32-timer";
117			reg = <0x40002000 0x400>;
118			interrupts = <45 0>;
119			interrupt-names = "global";
120			clocks = <&cctl GD32_CLOCK_TIMER13>;
121			resets = <&rctl GD32_RESET_TIMER13>;
122			channels = <1>;
123			status = "disabled";
124
125			pwm {
126				compatible = "gd,gd32-pwm";
127				status = "disabled";
128				#pwm-cells = <3>;
129			};
130		};
131	};
132};
133
134&flash0 {
135	reg = <0x08000000 DT_SIZE_K(512)>;
136};
137
138&sram0 {
139	reg = <0x20000000 DT_SIZE_K(128)>;
140};
141