1/* 2 * Copyright (c) 2022 Benjamin Björnsson <benjamin.bjornsson@gmail.com>. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <mem.h> 8 9/ { 10 leds { 11 compatible = "gpio-leds"; 12 red_led: led_0 { 13 gpios = <&gpiok 5 GPIO_ACTIVE_LOW>; 14 }; 15 green_led: led_1 { 16 gpios = <&gpiok 6 GPIO_ACTIVE_LOW>; 17 }; 18 blue_led: led_2 { 19 gpios = <&gpiok 7 GPIO_ACTIVE_LOW>; 20 }; 21 }; 22 23 otghs_ulpi_phy: otghs_ulpis_phy { 24 compatible = "usb-ulpi-phy"; 25 reset-gpios = < &gpioj 4 GPIO_ACTIVE_LOW >; 26 #phy-cells = <0>; 27 }; 28 29 aliases { 30 led0 = &red_led; 31 led1 = &green_led; 32 led2 = &blue_led; 33 }; 34}; 35 36&clk_hsi48 { 37 /* HSI48 required for USB */ 38 status = "okay"; 39}; 40 41&rcc { 42 d1cpre = < 1 >; 43 hpre = < 2 >; 44 d1ppre = < 2 >; 45 d2ppre1 = < 2 >; 46 d2ppre2 = < 2 >; 47 d3ppre = < 2 >; 48}; 49 50/* UART0 in datasheet */ 51&uart4 { 52 pinctrl-0 = <&uart4_tx_pa0 &uart4_rx_pi9>; 53 pinctrl-names = "default"; 54 current-speed = <115200>; 55}; 56 57/* UART1 in datasheet */ 58&usart1 { 59 pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>; 60 pinctrl-names = "default"; 61 current-speed = <115200>; 62}; 63 64/* UART2 in datasheet */ 65&usart6 { 66 pinctrl-0 = <&usart6_tx_pg14 &usart6_rx_pg9>; 67 pinctrl-names = "default"; 68 current-speed = <115200>; 69}; 70 71/* UART3 in datasheet */ 72&uart8 { 73 pinctrl-0 = <&uart8_tx_pj8 &uart8_rx_pj9>; 74 pinctrl-names = "default"; 75 current-speed = <115200>; 76}; 77 78/* I2C0 in datasheet */ 79&i2c3 { 80 pinctrl-0 = <&i2c3_scl_ph7 &i2c3_sda_ph8>; 81 pinctrl-names = "default"; 82 clock-frequency = <I2C_BITRATE_FAST>; 83}; 84 85/* I2C1 in datasheet */ 86&i2c1 { 87 pinctrl-0 = <&i2c1_scl_pb6 &i2c1_sda_pb7>; 88 pinctrl-names = "default"; 89 clock-frequency = <I2C_BITRATE_FAST>; 90}; 91 92/* I2C2 in datasheet */ 93&i2c4 { 94 pinctrl-0 = <&i2c4_scl_ph11 &i2c4_sda_ph12>; 95 pinctrl-names = "default"; 96 clock-frequency = <I2C_BITRATE_FAST>; 97}; 98 99/* I2C3 in datasheet */ 100&i2c3 { 101 pinctrl-0 = <&i2c3_scl_ph7 &i2c3_sda_ph8>; 102 pinctrl-names = "default"; 103 clock-frequency = <I2C_BITRATE_FAST>; 104}; 105 106/* SPI1 in datasheet */ 107&spi2 { 108 pinctrl-0 = <&spi2_nss_pi0 &spi2_sck_pi1 109 &spi2_miso_pc2 &spi2_mosi_pc3>; 110 pinctrl-names = "default"; 111}; 112 113&fdcan1 { 114 pinctrl-0 = <&fdcan1_rx_pb8 &fdcan1_tx_ph13>; 115 pinctrl-names = "default"; 116 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000100>, 117 <&rcc STM32_SRC_PLL1_Q FDCAN_SEL(1)>; 118}; 119 120&rtc { 121 status = "okay"; 122}; 123 124&mailbox { 125 status = "okay"; 126}; 127 128&fmc { 129 status = "okay"; 130 pinctrl-0 = < &fmc_d2_pd0 &fmc_d3_pd1 &fmc_d13_pd8 &fmc_d14_pd9 131 &fmc_d15_pd10 &fmc_d0_pd14 &fmc_d1_pd15 &fmc_nbl0_pe0 132 &fmc_nbl1_pe1 &fmc_d4_pe7 &fmc_d5_pe8 &fmc_d6_pe9 133 &fmc_d7_pe10 &fmc_d8_pe11 &fmc_d9_pe12 &fmc_d10_pe13 134 &fmc_d11_pe14 &fmc_d12_pe15 &fmc_a0_pf0 &fmc_a1_pf1 135 &fmc_a2_pf2 &fmc_a3_pf3 &fmc_a4_pf4 &fmc_a5_pf5 136 &fmc_sdnras_pf11 &fmc_a6_pf12 &fmc_a7_pf13 &fmc_a8_pf14 137 &fmc_a9_pf15 &fmc_a10_pg0 &fmc_a11_pg1 &fmc_a12_pg2 138 &fmc_a14_pg4 /* FMC_BA0 */ &fmc_a15_pg5 /* FMC_BA1 */ 139 &fmc_sdclk_pg8 &fmc_sdncas_pg15 &fmc_sdcke0_ph2 &fmc_sdne0_ph3 140 &fmc_sdnwe_ph5 >; 141 pinctrl-names = "default"; 142 st,mem-swap = "disable"; 143 sdram { 144 status = "okay"; 145 mode-register = < 0x220 >; 146 147 /** From Arduino github repository: 148 * RefreshRate = 64 ms / 8192 cyc = 7.8125 us/cyc 149 * RefreshCycles = 7.8125 us * 90 MHz = 703 150 * According to the formula on p.1665 of the reference manual, 151 * we also need to subtract 20 from the value, so the target 152 * refresh rate is 703 - 20 = 683. 153 */ 154 refresh-rate = < 683 >; 155 num-auto-refresh = < 8 >; 156 157 bank@0 { 158 reg = < 0 >; 159 st,sdram-control = < STM32_FMC_SDRAM_NC_8 160 STM32_FMC_SDRAM_NR_12 161 STM32_FMC_SDRAM_MWID_16 162 STM32_FMC_SDRAM_NB_4 163 STM32_FMC_SDRAM_CAS_2 164 STM32_FMC_SDRAM_SDCLK_PERIOD_2 165 STM32_FMC_SDRAM_RBURST_ENABLE 166 STM32_FMC_SDRAM_RPIPE_0 >; 167 st,sdram-timing = < 2 7 5 7 2 3 3 >; 168 }; 169 }; 170}; 171 172&quadspi { 173 pinctrl-0 = < &quadspi_bk1_io0_pd11 174 &quadspi_bk1_io1_pd12 175 &quadspi_bk1_io2_pf7 176 &quadspi_bk1_io3_pd13 177 &quadspi_bk1_ncs_pg6 178 &quadspi_clk_pf10 >; 179 pinctrl-names = "default"; 180 status = "okay"; 181 182 mx25l12833f: qspi-nor-flash@90000000 { 183 compatible = "st,stm32-qspi-nor"; 184 reg = < 0x90000000 DT_SIZE_M(16) >; /* 128 MBits */ 185 qspi-max-frequency = < 40000000 >; 186 sfdp-bfp = [ e5 20 f1 ff ff ff ff 07 44 eb 08 6b 08 3b 04 bb 187 fe ff ff ff ff ff 00 ff ff ff 44 eb 0c 20 0f 52 188 10 d8 00 ff 82 41 bd 00 81 e5 7b c6 44 03 67 38 189 30 b0 30 b0 f7 bd d5 5c 4a be 29 ff e1 d0 ff ff ]; 190 jedec-id = [ 66 66 20 ]; 191 spi-bus-width = <4>; 192 status = "okay"; 193 194 partitions { 195 compatible = "fixed-partitions"; 196 #address-cells = < 1 >; 197 #size-cells = < 1 >; 198 199 storage_partition: partition@0 { 200 label = "storage"; 201 reg=< 0x0 DT_SIZE_K(15872) >; 202 }; 203 204 wifi_firmware: partition@f80000 { 205 label = "wifi-firmware"; 206 reg = < 0xf80000 DT_SIZE_K(512) >; 207 }; 208 }; 209 }; 210}; 211 212&mac { 213 pinctrl-0 = < ð_ref_clk_pa1 214 ð_mdio_pa2 215 ð_crs_dv_pa7 216 ð_mdc_pc1 217 ð_rxd0_pc4 218 ð_rxd1_pc5 219 ð_tx_en_pg11 220 ð_txd1_pg12 221 ð_txd0_pg13 >; 222 pinctrl-names = "default"; 223}; 224 225zephyr_udc0: &usbotg_hs { 226 pinctrl-0 = < &usb_otg_hs_ulpi_d0_pa3 227 &usb_otg_hs_ulpi_ck_pa5 228 &usb_otg_hs_ulpi_d1_pb0 229 &usb_otg_hs_ulpi_d2_pb1 230 &usb_otg_hs_ulpi_d7_pb5 231 &usb_otg_hs_ulpi_d3_pb10 232 &usb_otg_hs_ulpi_d4_pb11 233 &usb_otg_hs_ulpi_d5_pb12 234 &usb_otg_hs_ulpi_d6_pb13 235 &usb_otg_hs_ulpi_stp_pc0 236 &usb_otg_hs_ulpi_nxt_ph4 237 &usb_otg_hs_ulpi_dir_pi11 >; 238 pinctrl-names = "default"; 239 phys = < &otghs_ulpi_phy >; 240 maximum-speed = "high-speed"; 241 /* Include the USB1ULPIEN | USB1OTGHSULPIEN clock enable bit */ 242 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x6000000>, 243 <&rcc STM32_SRC_HSI48 USB_SEL(3)>; 244 num-bidir-endpoints = < 4 >; 245 status = "okay"; 246}; 247
