1/*
2 * Copyright (c) 2020 Intel Corp.
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
6/* Pagetables. These are produced by arch/x86/gen-mmu.py based on
7 * data in zephyr_prebuilt.elf (the result of linker pass 1).
8 * For the pass 1 build, an equal-sized dummy area is provided as
9 * to not shift memory addresses that occur after this.
10 */
11#ifdef CONFIG_MMU
12    SECTION_DATA_PROLOGUE(pagetables,,)
13    {
14    . = ALIGN(4096);
15    z_x86_pagetables_start = .;
16#ifdef LINKER_ZEPHYR_FINAL
17    KEEP(*(pagetables))         /* gen_mmu.py */
18#else
19    KEEP(*(.dummy_pagetables))  /* from x86_mmu.c, just an empty array */
20#endif /* LINKER_ZEPHYR_FINAL */
21
22    /* Top-level paging structure is the last thing in this section */
23#if CONFIG_X86_PAE
24    /* 4-entry PDPT */
25    z_x86_kernel_ptables = . - 32;
26#else
27    /* Page directory or PML4 */
28    z_x86_kernel_ptables = . - 4096;
29#endif /* CONFIG_X86_PAE */
30    } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
31
32#ifdef LINKER_ZEPHYR_FINAL
33    /DISCARD/ :
34    {
35    /* We have the real ones in this build */
36    *(.dummy_pagetables)
37    }
38#endif /* LINKER_ZEPHYR_FINAL */
39#endif /* CONFIG_MMU */
40