1 /* 2 * Copyright (c) 2018 Lexmark International, Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_A_R_CPU_H_ 8 #define ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_A_R_CPU_H_ 9 10 #if defined(CONFIG_ARM_MPU) 11 #include <arch/arm/aarch32/cortex_a_r/mpu.h> 12 #endif 13 14 /* 15 * SCTRL register bit assignments 16 */ 17 #define SCTRL_MPU_ENABLE (1 << 0) 18 19 #define MODE_USR 0x10 20 #define MODE_FIQ 0x11 21 #define MODE_IRQ 0x12 22 #define MODE_SVC 0x13 23 #define MODE_ABT 0x17 24 #define MODE_UND 0x1b 25 #define MODE_SYS 0x1f 26 #define MODE_MASK 0x1f 27 28 #define A_BIT (1 << 8) 29 #define I_BIT (1 << 7) 30 #define F_BIT (1 << 6) 31 #define T_BIT (1 << 5) 32 33 #define HIVECS (1 << 13) 34 35 #define CPACR_NA (0U) 36 #define CPACR_FA (3U) 37 38 #define CPACR_CP10(r) (r << 20) 39 #define CPACR_CP11(r) (r << 22) 40 41 #define FPEXC_EN (1 << 30) 42 43 #define DFSR_DOMAIN_SHIFT (4) 44 #define DFSR_DOMAIN_MASK (0xf) 45 #define DFSR_FAULT_4_MASK (1 << 10) 46 #define DFSR_WRITE_MASK (1 << 11) 47 #define DFSR_AXI_SLAVE_MASK (1 << 12) 48 49 #endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_A_R_CPU_H_ */ 50
