1/*
2 * Copyright (c) 2018, Synopsys, Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include "skeleton.dtsi"
8
9#include <zephyr/dt-bindings/i2c/i2c.h>
10#include <zephyr/dt-bindings/gpio/gpio.h>
11
12/ {
13	cpus {
14		#address-cells = <1>;
15		#size-cells = <0>;
16
17		cpu0: cpu@0 {
18			device_type = "cpu";
19			compatible = "snps,arcem";
20			reg = <0>;
21		};
22	};
23
24	intc: arcv2-intc {
25		compatible = "snps,arcv2-intc";
26		interrupt-controller;
27		#interrupt-cells = <2>;
28	};
29
30	timer0: timer0 {
31		compatible = "snps,arc-timer";
32		interrupts = <16 1>;
33		interrupt-parent = <&intc>;
34	};
35
36	sysconf: system-configuration@f000a000 {
37		compatible = "snps,arc-iot-sysconf";
38		reg = <0xf000a000 0x90>;
39	};
40
41	iccm0: iccm@20000000 {
42		compatible = "arc,iccm";
43		reg = <0x20000000 0x40000>;
44	};
45
46	dccm0: dccm@80000000 {
47		compatible = "arc,dccm";
48		reg = <0x80000000 0x20000>;
49	};
50
51
52	sram: memory@30000000 {
53		compatible = "mmio-sram";
54		reg = <0x30000000 0x20000>;
55	};
56
57	flash0: flash@0 {
58		compatible = "soc-nv-flash";
59		reg = <0x0 0x40000>;
60	};
61
62	sysclk: system-clock {
63		compatible = "fixed-clock";
64		clock-frequency = <144000000>;
65		#clock-cells = <0>;
66	};
67
68	soc {
69		#address-cells = <1>;
70		#size-cells = <1>;
71		compatible = "simple-bus";
72		ranges;
73
74
75		uart0: uart@80014000 {
76			compatible = "ns16550";
77			clock-frequency = <16000000>;
78			reg = <0x80014000 0x100>;
79			interrupts = <86 0>;
80			interrupt-parent = <&intc>;
81			dlf = <0x01>;
82			reg-shift = <2>;
83		};
84
85		uart1: uart@80014100 {
86			compatible = "ns16550";
87			clock-frequency = <16000000>;
88			reg = <0x80014100 0x100>;
89			interrupts = <87 0>;
90			interrupt-parent = <&intc>;
91			reg-shift = <2>;
92			status = "disabled";
93		};
94
95		uart2: uart@80014200 {
96			compatible = "ns16550";
97			clock-frequency = <16000000>;
98			reg = <0x80014200 0x1000>;
99			interrupts = <88 0>;
100			interrupt-parent = <&intc>;
101			reg-shift = <2>;
102			status = "disabled";
103		};
104
105		uart3: uart@80014300 {
106			compatible = "ns16550";
107			clock-frequency = <144000000>;
108			reg = <0x80014300 0x100>;
109			interrupts = <89 0>;
110			interrupt-parent = <&intc>;
111			reg-shift = <2>;
112			status = "disabled";
113		};
114
115		gpio8b0: gpio@80017800 {
116			reg = <0x80017800 0x100>;
117			interrupts = <54 1>;
118			interrupt-parent = <&intc>;
119
120			gpio-controller;
121			#gpio-cells = <2>;
122
123			status = "disabled";
124		};
125
126		gpio8b1: gpio@80017900 {
127			reg = <0x80017900 0x100>;
128			interrupts = <55 1>;
129			interrupt-parent = <&intc>;
130
131			gpio-controller;
132			#gpio-cells = <2>;
133
134			status = "disabled";
135		};
136
137		gpio8b2: gpio@80017a00 {
138			reg = <0x80017a00 0x100>;
139			interrupts = <56 1>;
140			interrupt-parent = <&intc>;
141
142			gpio-controller;
143			#gpio-cells = <2>;
144
145			status = "disabled";
146		};
147
148		gpio8b3: gpio@80017b00 {
149			reg = <0x80017b00 0x100>;
150			interrupts = <57 1>;
151			interrupt-parent = <&intc>;
152
153			gpio-controller;
154			#gpio-cells = <2>;
155
156			status = "disabled";
157		};
158
159		gpio4b0: gpio@80017c00 {
160			reg = <0x80017c00 0x100>;
161			interrupts = <19 1>;
162			interrupt-parent = <&intc>;
163
164			gpio-controller;
165			#gpio-cells = <2>;
166		};
167
168		gpio4b1: gpio@80017d00 {
169			reg = <0x80017d00 0x100>;
170			interrupts = <52 1>;
171			interrupt-parent = <&intc>;
172
173			gpio-controller;
174			#gpio-cells = <2>;
175
176			status = "disabled";
177		};
178
179		gpio4b2: gpio@80017e00 {
180			reg = <0x80017e00 0x100>;
181			interrupts = <53 1>;
182			interrupt-parent = <&intc>;
183
184			gpio-controller;
185			#gpio-cells = <2>;
186
187			status = "disabled";
188		};
189
190
191		i2c0: i2c@80012000 {
192			clock-frequency = <I2C_BITRATE_STANDARD>;
193			#address-cells = <1>;
194			#size-cells = <0>;
195			reg = <0x80012000 0x100>;
196			interrupts = <58 1>, <61 1>, <60 1>, <59 1>;
197			interrupt-names = "error", "stop", "tx", "rx";
198			interrupt-parent = <&intc>;
199
200			status = "disabled";
201		};
202
203		i2c1: i2c@80012100 {
204			clock-frequency = <I2C_BITRATE_STANDARD>;
205			#address-cells = <1>;
206			#size-cells = <0>;
207			reg = <0x80012100 0x100>;
208			interrupts = <62 1>, <65 1>, <64 1>, <63 1>;
209			interrupt-names = "error", "stop", "tx", "rx";
210			interrupt-parent = <&intc>;
211
212			status = "disabled";
213		};
214
215		i2c2: i2c@80012200 {
216			clock-frequency = <I2C_BITRATE_STANDARD>;
217			#address-cells = <1>;
218			#size-cells = <0>;
219			reg = <0x80012200 0x100>;
220			interrupts = <66 1>, <69 1>, <68 1>, <67 1>;
221			interrupt-names = "error", "stop", "tx", "rx";
222			interrupt-parent = <&intc>;
223
224			status = "disabled";
225		};
226
227		spi0: spi@80010000 {
228			compatible = "snps,designware-spi";
229			#address-cells = <1>;
230			#size-cells = <0>;
231			reg = <0x80010000 0x100>;
232			clocks = <&sysclk>;
233			interrupts = <70 2>, <71 2>, <72 2>;
234			interrupt-names = "err-int", "rx-avail", "tx-req";
235			interrupt-parent = <&intc>;
236			status = "disabled";
237		};
238
239		spi1: spi@80010100 {
240			compatible = "snps,designware-spi";
241			#address-cells = <1>;
242			#size-cells = <0>;
243			reg = <0x80010100 0x100>;
244			clocks = <&sysclk>;
245			interrupts = <74 2>, <75 2>, <76 2>;
246			interrupt-names = "err-int", "rx-avail", "tx-req";
247			interrupt-parent = <&intc>;
248			status = "disabled";
249		};
250
251		spi2: spi@80010200 {
252			compatible = "snps,designware-spi";
253			#address-cells = <1>;
254			#size-cells = <0>;
255			reg = <0x80010200 0x100>;
256			clocks = <&sysclk>;
257			interrupts = <78 2>, <79 2>, <80 2>;
258			interrupt-names = "err-int", "rx-avail", "tx-req";
259			interrupt-parent = <&intc>;
260			status = "disabled";
261		};
262
263	};
264};
265