1.. _hardware_arch_arc_support_status:
2
3Zephyr support status on ARC processors
4#######################################
5
6Overview
7********
8
9This page describes current state of Zephyr for ARC processors and some future
10plans. Please note that
11
12 * plans are given without exact deadlines
13 * software features require corresponding hardware to be present and
14   configured the proper way
15 * not all the features can be enabled at the same time
16
17Support status
18**************
19
20Legend:
21**Y** - yes, supported; **N** - no, not supported; **WIP** - Work In Progress;
22**TBD** - to be decided
23
24
25+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
26|                                                                     | **Processor families**                                                 |
27+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
28|                                                                     | **EM**     | **HS3x/4x** | **VPX**           | **HS5x**   | **HS6x**   |
29+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
30| Port status                                                         | upstreamed | upstreamed  | upstreamed [#f6]_ | upstreamed | upstreamed |
31+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
32| **Features**                                                                                                                                 |
33+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
34| Closely coupled memories (ICCM, DCCM) [#f1]_                        | Y          | Y           | Y                 | TBD        | TBD        |
35+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
36| Execution with caches - Instruction/Data, L1/L2 caches              | Y          | Y           | Y                 | Y          | Y          |
37+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
38| Hardware-assisted unaligned memory access                           | Y [#f2]_   | Y           | Y                 | Y          | Y          |
39+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
40| Regular interrupts with multiple priority levels, direct interrupts | Y          | Y           | Y                 | Y          | Y          |
41+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
42| Fast interrupts, separate register banks for fast interrupts        | Y          | Y           | TBD               | N          | N          |
43+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
44| Hardware floating point unit (FPU)                                  | Y          | Y           | TBD [#f6]_        | TBD        | TBD        |
45+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
46| Symmetric multiprocessing (SMP) support, switch-based               | N/A        | Y           | TBD               | Y          | Y          |
47+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
48| Hardware-assisted stack checking                                    | Y          | Y           | Y                 | N          | N          |
49+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
50| Hardware-assisted atomic operations                                 | N/A        | Y           | Y                 | Y          | Y          |
51+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
52| DSP ISA                                                             | Y          | N [#f3]_    | TBD [#f6]_        | TBD        | TBD        |
53+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
54| DSP AGU/XY extensions                                               | Y          | N [#f3]_    | N/A               | TBD        | TBD        |
55+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
56| Userspace                                                           | Y          | Y           | N                 | TBD        | TBD        |
57+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
58| Memory protection unit (MPU)                                        | Y          | Y           | TBD               | N          | N          |
59+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
60| Memory management unit (MMU)                                        | N/A        | N           | TBD               | N          | N          |
61+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
62| SecureShield                                                        | Y          | N/A         | N/A               | N/A        | N/A        |
63+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
64| Single-thread kernel support [#f5]_                                 | Y          | Y           | Y                 | Y          | Y          |
65+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
66| **Toolchains**                                                                                                                               |
67+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
68| GNU (open source GCC-based)                                         | Y          | Y           | N                 | Y          | Y          |
69+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
70| MetaWare (proprietary Clang-based)                                  | Y          | Y           | Y                 | Y          | Y          |
71+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
72| **Simulators**                                                                                                                               |
73+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
74| QEMU (open source) [#f4]_                                           | Y          | Y           | N                 | Y          | Y          |
75+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
76| nSIM (proprietary, provided by MetaWare Development Tools)          | Y          | Y           | Y                 | Y          | Y          |
77+---------------------------------------------------------------------+------------+-------------+-------------------+------------+------------+
78
79Notes
80*****
81
82.. [#f1] usage of CCMs is limited on SMP systems
83.. [#f2] except the systems with secure features (SecureShield) due to HW
84         limitation
85.. [#f3] We only support save/restore ACCL/ACCH registers in task's context.
86         Rest of DSP/AGU registers save/restore isn't implemented but kernel
87         itself does not use these registers. This allows single task per
88         core to use DSP/AGU safely.
89.. [#f4] QEMU doesn't support all the ARC processor's HW features. For the
90         detailed info please check the ARC QEMU documentation
91.. [#f5] Single-thread kernel is support only for single core targets
92.. [#f6] currently only ARC VPX scalar port is supported. The support of VPX vector pipeline, VCCM,
93         STU is not included in this port, and require additional development and / or other runtime
94         integration.
95
96VPX Vector Registers
97--------------------
98Zephyr supports a limited form sharing of the VPX vector registers known as
99cooperative sharing. Threads that use these registers must bookend the relevant
100sections with calls to :c:func:`arc_vpx_lock` and :c:func:`arc_vpx_unlock` to
101control access to this resource.
102
103.. note::
104    If the system has multiple CPUs, then it is the responsibility of the
105    application developer to both pin the thread to a single CPU before it
106    attempts to get the cooperative lock, and not modify the CPU affinity
107    while it is waiting for or holding that cooperative lock.
108
109Configuration Options
110=====================
111
112The cooperative sharing of the VPX vector registers is selected when
113configuration option :kconfig:option:`CONFIG_ARC_VPX_COOPERATIVE_SHARING`
114is enabled.
115