1/*
2 * Copyright (c) 2023 Ambiq Micro Inc. <www.ambiq.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <dt-bindings/pinctrl/ambiq-apollo4-pinctrl.h>
8
9&pinctrl {
10	uart0_default: uart0_default {
11		group1 {
12			pinmux = <UART0TX_P12>;
13		};
14		group2 {
15			pinmux = <UART0RX_P47>;
16			input-enable;
17		};
18	};
19	itm_default: itm_default {
20		group1 {
21			pinmux = <SWO_P28>;
22		};
23	};
24	i2c0_default: i2c0_default {
25		group1 {
26			pinmux = <M0SCL_P5>, <M0SDAWIR3_P6>;
27			drive-open-drain;
28			drive-strength = "0.5";
29			bias-pull-up;
30		};
31	};
32	i2c1_default: i2c1_default {
33		group1 {
34			pinmux = <M1SCL_P8>, <M1SDAWIR3_P9>;
35			drive-open-drain;
36			drive-strength = "0.5";
37			bias-pull-up;
38		};
39	};
40	i2c2_default: i2c2_default {
41		group1 {
42			pinmux = <M2SCL_P25>, <M2SDAWIR3_P26>;
43			drive-open-drain;
44			drive-strength = "0.5";
45			bias-pull-up;
46		};
47	};
48	i2c3_default: i2c3_default {
49		group1 {
50			pinmux = <M3SCL_P31>, <M3SDAWIR3_P32>;
51			drive-open-drain;
52			drive-strength = "0.5";
53			bias-pull-up;
54		};
55	};
56	i2c5_default: i2c5_default {
57		group1 {
58			pinmux = <M5SCL_P47>, <M5SDAWIR3_P48>;
59			drive-open-drain;
60			drive-strength = "0.5";
61			bias-pull-up;
62		};
63	};
64	i2c6_default: i2c6_default {
65		group1 {
66			pinmux = <M6SCL_P61>, <M6SDAWIR3_P62>;
67			drive-open-drain;
68			drive-strength = "0.5";
69			bias-pull-up;
70		};
71	};
72	i2c7_default: i2c7_default {
73		group1 {
74			pinmux = <M7SCL_P22>, <M7SDAWIR3_P23>;
75			drive-open-drain;
76			drive-strength = "0.5";
77			bias-pull-up;
78		};
79	};
80
81	spi0_default: spi0_default {
82		group1 {
83			pinmux = <M0SCK_P5>, <M0MISO_P7>, <M0MOSI_P6>;
84		};
85	};
86	spi1_default: spi1_default {
87		group1 {
88			pinmux = <M1SCK_P8>, <M1MISO_P10>, <M1MOSI_P9>;
89		};
90	};
91	spi2_default: spi2_default {
92		group1 {
93			pinmux = <M2SCK_P25>, <M2MISO_P27>, <M2MOSI_P26>;
94		};
95	};
96	spi3_default: spi3_default {
97		group1 {
98			pinmux = <M3SCK_P31>, <M3MISO_P33>, <M3MOSI_P32>;
99		};
100	};
101	spi4_default: spi4_default {
102		group1 {
103			pinmux = <M4SCK_P34>, <M4MISO_P36>, <M4MOSI_P35>;
104		};
105	};
106	spi5_default: spi5_default {
107		group1 {
108			pinmux = <M5SCK_P47>, <M5MISO_P49>, <M5MOSI_P48>;
109		};
110	};
111	spi6_default: spi6_default {
112		group1 {
113			pinmux = <M6SCK_P61>, <M6MISO_P63>, <M6MOSI_P62>;
114		};
115	};
116	spi7_default: spi7_default {
117		group1 {
118			pinmux = <M7SCK_P22>, <M7MISO_P24>, <M7MOSI_P23>;
119		};
120	};
121	mspi0_default: mspi0_default{
122		group1 {
123			pinmux = <MSPI0_0_P64>,
124				 <MSPI0_1_P65>,
125				 <MSPI0_8_P72>;
126		};
127		group2 {
128			pinmux = <NCE57_P57>;
129			drive-push-pull;
130			drive-strength = "0.5";
131			ambiq,iom-nce-module = <32>;
132		};
133	};
134	mspi1_default: mspi1_default{
135		group1 {
136			pinmux = <MSPI1_0_P37>,
137				 <MSPI1_1_P38>,
138				 <MSPI1_8_P45>;
139		};
140		group2 {
141			pinmux = <NCE56_P56>;
142			drive-push-pull;
143			drive-strength = "0.5";
144			ambiq,iom-nce-module = <34>;
145		};
146	};
147	mspi2_default: mspi2_default{
148		group1 {
149			pinmux = <MSPI2_0_P74>,
150				 <MSPI2_1_P75>,
151				 <MSPI2_8_P82>;
152		};
153		group2 {
154			pinmux = <NCE52_P52>;
155			drive-push-pull;
156			drive-strength = "0.5";
157			ambiq,iom-nce-module = <36>;
158		};
159	};
160
161	xo32m_default: xo32m_default {
162		group1 {
163			pinmux = <CLKOUT_32M_P46>;
164			drive-strength = "0.1";
165		};
166	};
167	xo32k_default: xo32k_default {
168		group1 {
169			pinmux = <XT32KHZ_P4>;
170			drive-strength = "0.1";
171		};
172	};
173};
174