1 /*
2 * Copyright (c) 2023 Antmicro <www.antmicro.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT ambiq_stimer
8
9 /**
10 * @file
11 * @brief Ambiq Apollo STIMER-based sys_clock driver
12 *
13 */
14
15 #include <zephyr/init.h>
16 #include <zephyr/kernel.h>
17 #include <zephyr/drivers/timer/system_timer.h>
18 #include <zephyr/sys_clock.h>
19 #include <zephyr/irq.h>
20 #include <zephyr/spinlock.h>
21
22 /* ambiq-sdk includes */
23 #include <am_mcu_apollo.h>
24
25 #define COUNTER_MAX UINT32_MAX
26
27 #define CYC_PER_TICK (sys_clock_hw_cycles_per_sec() \
28 / CONFIG_SYS_CLOCK_TICKS_PER_SEC)
29 #define MAX_TICKS ((k_ticks_t)(COUNTER_MAX / CYC_PER_TICK) - 1)
30 #define MAX_CYCLES (MAX_TICKS * CYC_PER_TICK)
31 #define MIN_DELAY 1
32
33 #define TIMER_IRQ (DT_INST_IRQN(0))
34
35 #if defined(CONFIG_TEST)
36 const int32_t z_sys_timer_irq_for_test = TIMER_IRQ;
37 #endif
38
39 /* Value of STIMER counter when the previous kernel tick was announced */
40 static atomic_t g_last_count;
41
42 /* Spinlock to sync between Compare ISR and update of Compare register */
43 static struct k_spinlock g_lock;
44
stimer_isr(const void * arg)45 static void stimer_isr(const void *arg)
46 {
47 ARG_UNUSED(arg);
48
49 uint32_t irq_status = am_hal_stimer_int_status_get(false);
50
51 if (irq_status & AM_HAL_STIMER_INT_COMPAREA) {
52 am_hal_stimer_int_clear(AM_HAL_STIMER_INT_COMPAREA);
53
54 k_spinlock_key_t key = k_spin_lock(&g_lock);
55
56 uint32_t now = am_hal_stimer_counter_get();
57 uint32_t dticks = (uint32_t)((now - g_last_count) / CYC_PER_TICK);
58
59 g_last_count += dticks * CYC_PER_TICK;
60
61 if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
62 uint32_t next = g_last_count + CYC_PER_TICK;
63
64 if ((int32_t)(next - now) < MIN_DELAY) {
65 next += CYC_PER_TICK;
66 }
67 am_hal_stimer_compare_delta_set(0, next - g_last_count);
68 }
69
70 k_spin_unlock(&g_lock, key);
71 sys_clock_announce(dticks);
72 }
73 }
74
sys_clock_set_timeout(int32_t ticks,bool idle)75 void sys_clock_set_timeout(int32_t ticks, bool idle)
76 {
77 ARG_UNUSED(idle);
78
79 if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
80 return;
81 }
82
83 if (ticks == K_TICKS_FOREVER) {
84 return;
85 }
86
87 ticks = MIN(MAX_TICKS, ticks);
88 /* If tick is 0, set delta cyc to MIN_DELAY to trigger tick isr asap */
89 uint32_t cyc = MAX(ticks * CYC_PER_TICK, MIN_DELAY);
90
91 k_spinlock_key_t key = k_spin_lock(&g_lock);
92
93 am_hal_stimer_compare_delta_set(0, cyc);
94
95 k_spin_unlock(&g_lock, key);
96 }
97
sys_clock_elapsed(void)98 uint32_t sys_clock_elapsed(void)
99 {
100 if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
101 return 0;
102 }
103
104 k_spinlock_key_t key = k_spin_lock(&g_lock);
105 uint32_t ret = (am_hal_stimer_counter_get()
106 - g_last_count) / CYC_PER_TICK;
107
108 k_spin_unlock(&g_lock, key);
109 return ret;
110 }
111
sys_clock_cycle_get_32(void)112 uint32_t sys_clock_cycle_get_32(void)
113 {
114 return am_hal_stimer_counter_get();
115 }
116
stimer_init(void)117 static int stimer_init(void)
118 {
119 uint32_t oldCfg;
120 k_spinlock_key_t key = k_spin_lock(&g_lock);
121
122 oldCfg = am_hal_stimer_config(AM_HAL_STIMER_CFG_FREEZE);
123
124 am_hal_stimer_config((oldCfg & ~(AM_HAL_STIMER_CFG_FREEZE | STIMER_STCFG_CLKSEL_Msk))
125 | AM_HAL_STIMER_XTAL_32KHZ
126 | AM_HAL_STIMER_CFG_COMPARE_A_ENABLE);
127
128 g_last_count = am_hal_stimer_counter_get();
129
130 k_spin_unlock(&g_lock, key);
131
132 NVIC_ClearPendingIRQ(TIMER_IRQ);
133 IRQ_CONNECT(TIMER_IRQ, 0, stimer_isr, 0, 0);
134 irq_enable(TIMER_IRQ);
135
136 am_hal_stimer_int_enable(AM_HAL_STIMER_INT_COMPAREA);
137 /* Start timer with period CYC_PER_TICK if tickless is not enabled */
138 if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
139 am_hal_stimer_compare_delta_set(0, CYC_PER_TICK);
140 }
141 return 0;
142 }
143
144 SYS_INIT(stimer_init, PRE_KERNEL_2,
145 CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
146
