1/* SPDX-License-Identifier: Apache-2.0 */
2
3#include <arm/armv7-m.dtsi>
4#include <mem.h>
5#include <freq.h>
6#include <zephyr/dt-bindings/i2c/i2c.h>
7#include <zephyr/dt-bindings/gpio/gpio.h>
8
9/ {
10	clocks {
11		uartclk: apb-pclk {
12			compatible = "fixed-clock";
13			clock-frequency = <DT_FREQ_M(24)>;
14			#clock-cells = <0>;
15		};
16	};
17
18	cpus {
19		#address-cells = <1>;
20		#size-cells = <0>;
21
22		cpu0: cpu@0 {
23			compatible = "arm,cortex-m4f";
24			reg = <0>;
25		};
26	};
27
28	/* MRAM region */
29	flash0: flash@18000 {
30		compatible = "soc-nv-flash";
31		reg = <0x00018000 0x1e8000>;
32	};
33
34	/* TCM */
35	tcm: tcm@10000000 {
36		compatible = "zephyr,memory-region";
37		reg = <0x10000000 0x10000>;
38		zephyr,memory-region = "ITCM";
39	};
40
41	/* SRAM */
42	sram0: memory@10010000 {
43		compatible = "mmio-sram";
44		reg = <0x10010000 0x2B0000>;
45	};
46
47	soc {
48		compatible = "ambiq,apollo4p", "ambiq,apollo4x", "simple-bus";
49
50		pwrcfg: pwrcfg@40021000 {
51			compatible = "ambiq,pwrctrl";
52			reg = <0x40021000 0x400>;
53			#pwrcfg-cells = <2>;
54		};
55
56		stimer0: stimer@40008800 {
57			compatible = "ambiq,stimer";
58			reg = <0x40008800 0x80>;
59			interrupts = <32 0>;
60			status = "okay";
61		};
62
63		counter0: counter@40008000 {
64			compatible = "ambiq,counter";
65			reg = <0x40008000 0x80>;
66			interrupts = <67 0>;
67			status = "disabled";
68		};
69
70		uart0: uart@4001c000 {
71			compatible = "ambiq,uart", "arm,pl011";
72			reg = <0x4001c000 0x1000>;
73			interrupts = <15 0>;
74			interrupt-names = "UART0";
75			status = "disabled";
76			clocks = <&uartclk>;
77			ambiq,pwrcfg = <&pwrcfg 0x4 0x200>;
78		};
79		uart1: uart@4001d000 {
80			compatible = "ambiq,uart", "arm,pl011";
81			reg = <0x4001d000 0x1000>;
82			interrupts = <16 0>;
83			interrupt-names = "UART1";
84			status = "disabled";
85			clocks = <&uartclk>;
86			ambiq,pwrcfg = <&pwrcfg 0x4 0x400>;
87		};
88
89		uart2: uart@4001e000 {
90			compatible = "ambiq,uart", "arm,pl011";
91			reg = <0x4001e000 0x1000>;
92			interrupts = <17 0>;
93			interrupt-names = "UART2";
94			status = "disabled";
95			clocks = <&uartclk>;
96			ambiq,pwrcfg = <&pwrcfg 0x4 0x800>;
97		};
98
99		uart3: uart@4001f000 {
100			compatible = "ambiq,uart", "arm,pl011";
101			reg = <0x4001f000 0x1000>;
102			interrupts = <18 0>;
103			interrupt-names = "UART3";
104			status = "disabled";
105			clocks = <&uartclk>;
106			ambiq,pwrcfg = <&pwrcfg 0x4 0x1000>;
107		};
108
109		iom0_spi: spi@40050000 {
110			reg = <0x40050000 0x1000>;
111			#address-cells = <1>;
112			#size-cells = <0>;
113			interrupts = <6 0>;
114			status = "disabled";
115			ambiq,pwrcfg = <&pwrcfg 0x4 0x2>;
116		};
117
118		iom0_i2c: i2c@40050000 {
119			reg = <0x40050000 0x1000>;
120			#address-cells = <1>;
121			#size-cells = <0>;
122			interrupts = <6 0>;
123			status = "disabled";
124			ambiq,pwrcfg = <&pwrcfg 0x4 0x2>;
125		};
126
127		iom1_spi: spi@40051000 {
128			reg = <0x40051000 0x1000>;
129			#address-cells = <1>;
130			#size-cells = <0>;
131			interrupts = <7 0>;
132			status = "disabled";
133			ambiq,pwrcfg = <&pwrcfg 0x4 0x4>;
134		};
135
136		iom1_i2c: i2c@40051000 {
137			reg = <0x40051000 0x1000>;
138			#address-cells = <1>;
139			#size-cells = <0>;
140			interrupts = <7 0>;
141			status = "disabled";
142			ambiq,pwrcfg = <&pwrcfg 0x4 0x4>;
143		};
144
145		iom2_spi: spi@40052000 {
146			reg = <0x40052000 0x1000>;
147			#address-cells = <1>;
148			#size-cells = <0>;
149			interrupts = <8 0>;
150			status = "disabled";
151			ambiq,pwrcfg = <&pwrcfg 0x4 0x8>;
152		};
153
154		iom2_i2c: i2c@40052000 {
155			reg = <0x40052000 0x1000>;
156			#address-cells = <1>;
157			#size-cells = <0>;
158			interrupts = <8 0>;
159			status = "disabled";
160			ambiq,pwrcfg = <&pwrcfg 0x4 0x8>;
161		};
162
163		iom3_spi: spi@40053000 {
164			reg = <0x40053000 0x1000>;
165			#address-cells = <1>;
166			#size-cells = <0>;
167			interrupts = <9 0>;
168			status = "disabled";
169			ambiq,pwrcfg = <&pwrcfg 0x4 0x10>;
170		};
171
172		iom3_i2c: i2c@40053000 {
173			reg = <0x40053000 0x1000>;
174			#address-cells = <1>;
175			#size-cells = <0>;
176			interrupts = <9 0>;
177			status = "disabled";
178			ambiq,pwrcfg = <&pwrcfg 0x4 0x10>;
179		};
180
181		iom4_spi: spi@40054000 {
182			reg = <0x40054000 0x1000>;
183			#address-cells = <1>;
184			#size-cells = <0>;
185			interrupts = <10 0>;
186			status = "disabled";
187			ambiq,pwrcfg = <&pwrcfg 0x4 0x20>;
188		};
189
190		iom4_i2c: i2c@40054000 {
191			reg = <0x40054000 0x1000>;
192			#address-cells = <1>;
193			#size-cells = <0>;
194			interrupts = <10 0>;
195			status = "disabled";
196			ambiq,pwrcfg = <&pwrcfg 0x4 0x20>;
197		};
198
199		iom5_spi: spi@40055000 {
200			reg = <0x40055000 0x1000>;
201			#address-cells = <1>;
202			#size-cells = <0>;
203			interrupts = <11 0>;
204			status = "disabled";
205			ambiq,pwrcfg = <&pwrcfg 0x4 0x40>;
206		};
207
208		iom5_i2c: i2c@40055000 {
209			reg = <0x40055000 0x1000>;
210			#address-cells = <1>;
211			#size-cells = <0>;
212			interrupts = <11 0>;
213			status = "disabled";
214			ambiq,pwrcfg = <&pwrcfg 0x4 0x40>;
215		};
216
217		iom6_spi: spi@40056000 {
218			reg = <0x40056000 0x1000>;
219			#address-cells = <1>;
220			#size-cells = <0>;
221			interrupts = <12 0>;
222			status = "disabled";
223			ambiq,pwrcfg = <&pwrcfg 0x4 0x80>;
224		};
225
226		iom6_i2c: i2c@40056000 {
227			reg = <0x40056000 0x1000>;
228			#address-cells = <1>;
229			#size-cells = <0>;
230			interrupts = <12 0>;
231			status = "disabled";
232			ambiq,pwrcfg = <&pwrcfg 0x4 0x80>;
233		};
234
235		iom7_spi: spi@40057000 {
236			reg = <0x40057000 0x1000>;
237			#address-cells = <1>;
238			#size-cells = <0>;
239			interrupts = <13 0>;
240			status = "disabled";
241			ambiq,pwrcfg = <&pwrcfg 0x4 0x100>;
242		};
243
244		iom7_i2c: i2c@40057000 {
245			reg = <0x40057000 0x1000>;
246			#address-cells = <1>;
247			#size-cells = <0>;
248			interrupts = <13 0>;
249			status = "disabled";
250			ambiq,pwrcfg = <&pwrcfg 0x4 0x100>;
251		};
252
253		mspi0: spi@40060000 {
254			compatible = "ambiq,mspi";
255			reg = <0x40060000 0x400>;
256			interrupts = <20 0>;
257			#address-cells = <1>;
258			#size-cells = <0>;
259			status = "disabled";
260			ambiq,pwrcfg = <&pwrcfg 0x4 0x4000>;
261		};
262
263		mspi1: spi@40061000 {
264			compatible = "ambiq,mspi";
265			reg = <0x40061000 0x400>;
266			interrupts = <21 0>;
267			#address-cells = <1>;
268			#size-cells = <0>;
269			status = "disabled";
270			ambiq,pwrcfg = <&pwrcfg 0x4 0x8000>;
271		};
272
273		mspi2: spi@40062000 {
274			compatible = "ambiq,mspi";
275			reg = <0x40062000 0x400>;
276			interrupts = <22 0>;
277			#address-cells = <1>;
278			#size-cells = <0>;
279			status = "disabled";
280			ambiq,pwrcfg = <&pwrcfg 0x4 0x10000>;
281		};
282
283		pinctrl: pin-controller@40010000 {
284			compatible = "ambiq,apollo4-pinctrl";
285			reg = <0x40010000 0x800>;
286			#address-cells = <1>;
287			#size-cells = <0>;
288
289			gpio: gpio@40010000 {
290				compatible = "ambiq,gpio";
291				gpio-map-mask = <0xffffffe0 0xffffffc0>;
292				gpio-map-pass-thru = <0x1f 0x3f>;
293				gpio-map = <
294					0x00 0x0 &gpio0_31 0x0 0x0
295					0x20 0x0 &gpio32_63 0x0 0x0
296					0x40 0x0 &gpio64_95 0x0 0x0
297					0x60 0x0 &gpio96_127 0x0 0x0
298				>;
299				reg = <0x40010000>;
300				#gpio-cells = <2>;
301				#address-cells = <1>;
302				#size-cells = <0>;
303				ranges;
304
305				gpio0_31: gpio0_31@0 {
306					compatible = "ambiq,gpio-bank";
307					gpio-controller;
308					#gpio-cells = <2>;
309					reg = <0>;
310					interrupts = <56 0>;
311					status = "disabled";
312				};
313
314				gpio32_63: gpio32_63@80 {
315					compatible = "ambiq,gpio-bank";
316					gpio-controller;
317					#gpio-cells = <2>;
318					reg = <0x80>;
319					interrupts = <57 0>;
320					status = "disabled";
321				};
322
323				gpio64_95: gpio64_95@100 {
324					compatible = "ambiq,gpio-bank";
325					gpio-controller;
326					#gpio-cells = <2>;
327					reg = <0x100>;
328					interrupts = <58 0>;
329					status = "disabled";
330				};
331
332				gpio96_127: gpio96_127@180 {
333					compatible = "ambiq,gpio-bank";
334					gpio-controller;
335					#gpio-cells = <2>;
336					reg = <0x180>;
337					interrupts = <59 0>;
338					status = "disabled";
339				};
340			};
341		};
342
343		wdt0: watchdog@40024000 {
344			compatible = "ambiq,watchdog";
345			reg = <0x40024000 0x400>;
346			interrupts = <1 0>;
347			clock-frequency = <16>;
348			status = "disabled";
349		};
350	};
351};
352
353&nvic {
354	arm,num-irq-priority-bits = <3>;
355};
356