1/* SPDX-License-Identifier: Apache-2.0 */
2
3#include <arm/armv7-m.dtsi>
4#include <mem.h>
5#include <freq.h>
6#include <zephyr/dt-bindings/i2c/i2c.h>
7#include <zephyr/dt-bindings/gpio/gpio.h>
8
9/ {
10	clocks {
11		uartclk: apb-pclk {
12			compatible = "fixed-clock";
13			clock-frequency = <DT_FREQ_M(24)>;
14			#clock-cells = <0>;
15		};
16	};
17
18	cpus {
19		#address-cells = <1>;
20		#size-cells = <0>;
21
22		cpu0: cpu@0 {
23			compatible = "arm,cortex-m4f";
24			reg = <0>;
25		};
26	};
27
28	/* TCM */
29	tcm: tcm@10000000 {
30		compatible = "zephyr,memory-region";
31		reg = <0x10000000 0x10000>;
32		zephyr,memory-region = "ITCM";
33	};
34
35	/* SRAM */
36	sram0: memory@10010000 {
37		compatible = "mmio-sram";
38		reg = <0x10010000 0x50000>;
39	};
40
41	soc {
42		compatible = "ambiq,apollo3-blue", "ambiq,apollo3x", "simple-bus";
43
44		flash: flash-controller@c000 {
45			compatible = "ambiq,flash-controller";
46			reg = <0x0000c000 0xf4000>;
47
48			#address-cells = <1>;
49			#size-cells = <1>;
50
51			/* Flash region */
52			flash0: flash@c000 {
53				compatible = "soc-nv-flash";
54				reg = <0x0000c000 0xf4000>;
55			};
56		};
57
58		pwrcfg: pwrcfg@40021000 {
59			compatible = "ambiq,pwrctrl";
60			reg = <0x40021000 0x400>;
61			#pwrcfg-cells = <2>;
62		};
63
64		stimer0: stimer@40008140 {
65			compatible = "ambiq,stimer";
66			reg = <0x40008140 0x80>;
67			interrupts = <23 0>;
68			status = "okay";
69		};
70
71		counter0: counter@40008000 {
72			compatible = "ambiq,counter";
73			reg = <0x40008000 0x20>;
74			interrupts = <14 0>;
75			clock-frequency = <DT_FREQ_M(3)>;
76			clk-source = <2>;
77			status = "disabled";
78		};
79
80		counter1: counter@40008020 {
81			compatible = "ambiq,counter";
82			reg = <0x40008020 0x20>;
83			interrupts = <14 0>;
84			clock-frequency = <DT_FREQ_M(3)>;
85			clk-source = <2>;
86			status = "disabled";
87		};
88
89		counter2: counter@40008040 {
90			compatible = "ambiq,counter";
91			reg = <0x40008040 0x20>;
92			interrupts = <14 0>;
93			clock-frequency = <DT_FREQ_M(3)>;
94			clk-source = <2>;
95			status = "disabled";
96		};
97
98		counter3: counter@40008060 {
99			compatible = "ambiq,counter";
100			reg = <0x40008060 0x20>;
101			interrupts = <14 0>;
102			clock-frequency = <DT_FREQ_M(3)>;
103			clk-source = <2>;
104			status = "disabled";
105		};
106
107		counter4: counter@40008080 {
108			compatible = "ambiq,counter";
109			reg = <0x40008080 0x20>;
110			interrupts = <14 0>;
111			clock-frequency = <DT_FREQ_M(3)>;
112			clk-source = <2>;
113			status = "disabled";
114		};
115
116		counter5: counter@400080a0 {
117			compatible = "ambiq,counter";
118			reg = <0x400080A0 0x20>;
119			interrupts = <14 0>;
120			clock-frequency = <DT_FREQ_M(3)>;
121			clk-source = <2>;
122			status = "disabled";
123		};
124
125		counter6: counter@400080c0 {
126			compatible = "ambiq,counter";
127			reg = <0x400080C0 0x20>;
128			interrupts = <14 0>;
129			clock-frequency = <DT_FREQ_M(3)>;
130			clk-source = <2>;
131			status = "disabled";
132		};
133
134		counter7: counter@400080e0 {
135			compatible = "ambiq,counter";
136			reg = <0x400080E0 0x20>;
137			interrupts = <14 0>;
138			clock-frequency = <DT_FREQ_M(3)>;
139			clk-source = <2>;
140			status = "disabled";
141		};
142
143		uart0: uart@4001c000 {
144			compatible = "ambiq,uart", "arm,pl011";
145			reg = <0x4001c000 0x1000>;
146			interrupts = <15 0>;
147			interrupt-names = "UART0";
148			status = "disabled";
149			clocks = <&uartclk>;
150			ambiq,pwrcfg = <&pwrcfg 0x8 0x80>;
151		};
152
153		uart1: uart@4001d000 {
154			compatible = "ambiq,uart", "arm,pl011";
155			reg = <0x4001d000 0x1000>;
156			interrupts = <16 0>;
157			interrupt-names = "UART1";
158			status = "disabled";
159			clocks = <&uartclk>;
160			ambiq,pwrcfg = <&pwrcfg 0x8 0x100>;
161		};
162
163		spi0: spi@50004000 {
164			reg = <0x50004000 0x1000>;
165			#address-cells = <1>;
166			#size-cells = <0>;
167			interrupts = <6 0>;
168			status = "disabled";
169			ambiq,pwrcfg = <&pwrcfg 0x8 0x2>;
170		};
171
172		spi1: spi@50005000 {
173			reg = <0x50005000 0x1000>;
174			#address-cells = <1>;
175			#size-cells = <0>;
176			interrupts = <7 0>;
177			status = "disabled";
178			ambiq,pwrcfg = <&pwrcfg 0x8 0x4>;
179		};
180
181		spi2: spi@50006000 {
182			reg = <0x50006000 0x1000>;
183			#address-cells = <1>;
184			#size-cells = <0>;
185			interrupts = <8 0>;
186			status = "disabled";
187			ambiq,pwrcfg = <&pwrcfg 0x8 0x8>;
188		};
189
190		spi3: spi@50007000 {
191			reg = <0x50007000 0x1000>;
192			#address-cells = <1>;
193			#size-cells = <0>;
194			interrupts = <9 0>;
195			status = "disabled";
196			ambiq,pwrcfg = <&pwrcfg 0x8 0x10>;
197		};
198
199		spi4: spi@50008000 {
200			reg = <0x50008000 0x1000>;
201			#address-cells = <1>;
202			#size-cells = <0>;
203			interrupts = <10 0>;
204			status = "disabled";
205			ambiq,pwrcfg = <&pwrcfg 0x8 0x20>;
206		};
207
208		spi5: spi@50009000 {
209			reg = <0x50009000 0x1000>;
210			#address-cells = <1>;
211			#size-cells = <0>;
212			interrupts = <11 0>;
213			status = "disabled";
214			ambiq,pwrcfg = <&pwrcfg 0x8 0x40>;
215		};
216
217		i2c0: i2c@50004000 {
218			reg = <0x50004000 0x1000>;
219			#address-cells = <1>;
220			#size-cells = <0>;
221			interrupts = <6 0>;
222			status = "disabled";
223			ambiq,pwrcfg = <&pwrcfg 0x8 0x2>;
224		};
225
226		i2c1: i2c@50005000 {
227			reg = <0x50005000 0x1000>;
228			#address-cells = <1>;
229			#size-cells = <0>;
230			interrupts = <7 0>;
231			status = "disabled";
232			ambiq,pwrcfg = <&pwrcfg 0x8 0x4>;
233		};
234
235		i2c2: i2c@50006000 {
236			reg = <0x50006000 0x1000>;
237			#address-cells = <1>;
238			#size-cells = <0>;
239			interrupts = <8 0>;
240			status = "disabled";
241			ambiq,pwrcfg = <&pwrcfg 0x8 0x8>;
242		};
243
244		i2c3: i2c@50007000 {
245			reg = <0x50007000 0x1000>;
246			#address-cells = <1>;
247			#size-cells = <0>;
248			interrupts = <9 0>;
249			status = "disabled";
250			ambiq,pwrcfg = <&pwrcfg 0x8 0x10>;
251		};
252
253		i2c4: i2c@50008000 {
254			reg = <0x50008000 0x1000>;
255			#address-cells = <1>;
256			#size-cells = <0>;
257			interrupts = <10 0>;
258			status = "disabled";
259			ambiq,pwrcfg = <&pwrcfg 0x8 0x20>;
260		};
261
262		i2c5: i2c@50009000 {
263			reg = <0x50009000 0x1000>;
264			#address-cells = <1>;
265			#size-cells = <0>;
266			interrupts = <11 0>;
267			status = "disabled";
268			ambiq,pwrcfg = <&pwrcfg 0x8 0x40>;
269		};
270
271		mspi0: spi@40020000 {
272			compatible = "ambiq,mspi";
273			reg = <0x40020000 0x400>;
274			interrupts = <20 0>;
275			#address-cells = <1>;
276			#size-cells = <0>;
277			status = "disabled";
278			ambiq,pwrcfg = <&pwrcfg 0x8 0x800>;
279		};
280
281		bleif: spi@5000c000 {
282			compatible = "ambiq,spi-bleif";
283			reg = <0x5000c000 0x414>;
284			interrupts = <12 1>;
285			#address-cells = <1>;
286			#size-cells = <0>;
287			status = "disabled";
288			ambiq,pwrcfg = <&pwrcfg 0x8 0x8000>;
289
290			bt_hci_apollo: bt-hci@0 {
291				compatible = "ambiq,bt-hci-spi";
292				spi-max-frequency = <DT_FREQ_M(6)>;
293				reg = <0>;
294			};
295		};
296
297		pinctrl: pin-controller@40010000 {
298			compatible = "ambiq,apollo3-pinctrl";
299			reg = <0x40010000 0x800>;
300			#address-cells = <1>;
301			#size-cells = <0>;
302
303			gpio: gpio@40010000 {
304				compatible = "ambiq,gpio";
305				gpio-map-mask = <0xffffffe0 0xffffffc0>;
306				gpio-map-pass-thru = <0x1f 0x3f>;
307				gpio-map = <
308					0x00 0x0 &gpio0_31 0x0 0x0
309					0x20 0x0 &gpio32_63 0x0 0x0
310				>;
311				reg = <0x40010000>;
312				#gpio-cells = <2>;
313				#address-cells = <1>;
314				#size-cells = <0>;
315				ranges;
316
317				gpio0_31: gpio0_31@0 {
318					compatible = "ambiq,gpio-bank";
319					gpio-controller;
320					#gpio-cells = <2>;
321					reg = <0>;
322					interrupts = <13 0>;
323					status = "disabled";
324				};
325
326				gpio32_63: gpio32_63@20 {
327					compatible = "ambiq,gpio-bank";
328					gpio-controller;
329					#gpio-cells = <2>;
330					reg = <0x20>;
331					interrupts = <13 0>;
332					status = "disabled";
333					ngpios = <18>;
334				};
335			};
336		};
337
338		wdt0: watchdog@40024000 {
339			compatible = "ambiq,watchdog";
340			reg = <0x40024000 0x400>;
341			interrupts = <1 0>;
342			clock-frequency = <16>;
343			status = "disabled";
344		};
345	};
346};
347
348&nvic {
349	arm,num-irq-priority-bits = <3>;
350};
351