1 //***************************************************************************** 2 // 3 //! @file am_hal_pwrctrl_helper.h 4 //! 5 //! @brief Internal definitions for Power Control 6 //! 7 //! @addtogroup pwrctrl3p Pwrctrl - Power Control 8 //! @ingroup apollo3p_hal 9 //! @{ 10 // 11 //***************************************************************************** 12 13 //***************************************************************************** 14 // 15 // Copyright (c) 2023, Ambiq Micro, Inc. 16 // All rights reserved. 17 // 18 // Redistribution and use in source and binary forms, with or without 19 // modification, are permitted provided that the following conditions are met: 20 // 21 // 1. Redistributions of source code must retain the above copyright notice, 22 // this list of conditions and the following disclaimer. 23 // 24 // 2. Redistributions in binary form must reproduce the above copyright 25 // notice, this list of conditions and the following disclaimer in the 26 // documentation and/or other materials provided with the distribution. 27 // 28 // 3. Neither the name of the copyright holder nor the names of its 29 // contributors may be used to endorse or promote products derived from this 30 // software without specific prior written permission. 31 // 32 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 33 // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 36 // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 37 // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 38 // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 39 // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 40 // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 41 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 42 // POSSIBILITY OF SUCH DAMAGE. 43 // 44 // This is part of revision release_sdk_3_1_1-10cda4b5e0 of the AmbiqSuite Development Package. 45 // 46 //***************************************************************************** 47 48 #ifndef AM_HAL_PWRCTRL_INTERNAL_H 49 #define AM_HAL_PWRCTRL_INTERNAL_H 50 51 //***************************************************************************** 52 // 53 //! Peripheral enable bits for am_hal_pwrctrl_periph_enable/disable() 54 // 55 //***************************************************************************** 56 #define AM_HAL_PWRCTRL_IOS (_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOS, PWRCTRL_DEVPWREN_PWRIOS_EN)) 57 #define AM_HAL_PWRCTRL_IOM0 (_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOM0, PWRCTRL_DEVPWREN_PWRIOM0_EN)) 58 #define AM_HAL_PWRCTRL_IOM1 (_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOM1, PWRCTRL_DEVPWREN_PWRIOM1_EN)) 59 #define AM_HAL_PWRCTRL_IOM2 (_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOM2, PWRCTRL_DEVPWREN_PWRIOM2_EN)) 60 #define AM_HAL_PWRCTRL_IOM3 (_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOM3, PWRCTRL_DEVPWREN_PWRIOM3_EN)) 61 #define AM_HAL_PWRCTRL_IOM4 (_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOM4, PWRCTRL_DEVPWREN_PWRIOM4_EN)) 62 #define AM_HAL_PWRCTRL_IOM5 (_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOM5, PWRCTRL_DEVPWREN_PWRIOM5_EN)) 63 #define AM_HAL_PWRCTRL_UART0 (_VAL2FLD(PWRCTRL_DEVPWREN_PWRUART0, PWRCTRL_DEVPWREN_PWRUART0_EN)) 64 #define AM_HAL_PWRCTRL_UART1 (_VAL2FLD(PWRCTRL_DEVPWREN_PWRUART1, PWRCTRL_DEVPWREN_PWRUART1_EN)) 65 #define AM_HAL_PWRCTRL_ADC (_VAL2FLD(PWRCTRL_DEVPWREN_PWRADC, PWRCTRL_DEVPWREN_PWRADC_EN)) 66 #define AM_HAL_PWRCTRL_SCARD (_VAL2FLD(PWRCTRL_DEVPWREN_PWRSCARD, PWRCTRL_DEVPWREN_PWRSCARD_EN)) 67 #define AM_HAL_PWRCTRL_MSPI0 (_VAL2FLD(PWRCTRL_DEVPWREN_PWRMSPI0, PWRCTRL_DEVPWREN_PWRMSPI_EN)) 68 #define AM_HAL_PWRCTRL_MSPI1 (_VAL2FLD(PWRCTRL_DEVPWREN_PWRMSPI1, PWRCTRL_DEVPWREN_PWRMSPI_EN)) 69 #define AM_HAL_PWRCTRL_MSPI2 (_VAL2FLD(PWRCTRL_DEVPWREN_PWRMSPI2, PWRCTRL_DEVPWREN_PWRMSPI_EN)) 70 #define AM_HAL_PWRCTRL_PDM (_VAL2FLD(PWRCTRL_DEVPWREN_PWRPDM, PWRCTRL_DEVPWREN_PWRPDM_EN)) 71 #define AM_HAL_PWRCTRL_BLEL (_VAL2FLD(PWRCTRL_DEVPWREN_PWRBLEL, PWRCTRL_DEVPWREN_PWRBLEL_EN)) 72 73 #define AM_HAL_PWRCTRL_DEVPWREN_MASK 0x0000FFFF 74 #define AM_HAL_PWRCTRL_DEVPWRSTATUS_MASK 0x000003FC 75 76 //***************************************************************************** 77 // 78 //! Memory enable values for all defined memory configurations. 79 // 80 //***************************************************************************** 81 #define AM_HAL_PWRCTRL_MEMEN_SRAM_8K_DTCM (_VAL2FLD(PWRCTRL_MEMPWREN_DTCM, PWRCTRL_MEMPWREN_DTCM_GROUP0DTCM0)) 82 #define AM_HAL_PWRCTRL_MEMEN_SRAM_32K_DTCM (_VAL2FLD(PWRCTRL_MEMPWREN_DTCM, PWRCTRL_MEMPWREN_DTCM_GROUP0)) 83 #define AM_HAL_PWRCTRL_MEMEN_SRAM_64K_DTCM (_VAL2FLD(PWRCTRL_MEMPWREN_DTCM, PWRCTRL_MEMPWREN_DTCM_ALL)) 84 #define AM_HAL_PWRCTRL_MEMEN_SRAM_128K \ 85 (AM_HAL_PWRCTRL_MEMEN_SRAM_64K_DTCM | \ 86 _VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_GROUP0)) 87 #define AM_HAL_PWRCTRL_MEMEN_SRAM_192K \ 88 (AM_HAL_PWRCTRL_MEMEN_SRAM_128K | \ 89 _VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_GROUP1)) 90 #define AM_HAL_PWRCTRL_MEMEN_SRAM_256K \ 91 (AM_HAL_PWRCTRL_MEMEN_SRAM_192K | \ 92 _VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_GROUP2)) 93 #define AM_HAL_PWRCTRL_MEMEN_SRAM_320K \ 94 (AM_HAL_PWRCTRL_MEMEN_SRAM_256K | \ 95 _VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_GROUP3)) 96 #define AM_HAL_PWRCTRL_MEMEN_SRAM_384K \ 97 (AM_HAL_PWRCTRL_MEMEN_SRAM_320K | \ 98 _VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_GROUP4)) 99 #define AM_HAL_PWRCTRL_MEMEN_SRAM_448K \ 100 (AM_HAL_PWRCTRL_MEMEN_SRAM_384K | \ 101 _VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_GROUP5)) 102 #define AM_HAL_PWRCTRL_MEMEN_SRAM_512K \ 103 (AM_HAL_PWRCTRL_MEMEN_SRAM_448K | \ 104 _VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_GROUP6)) 105 #define AM_HAL_PWRCTRL_MEMEN_SRAM_576K \ 106 (AM_HAL_PWRCTRL_MEMEN_SRAM_512K | \ 107 _VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_GROUP7)) 108 #define AM_HAL_PWRCTRL_MEMEN_SRAM_672K \ 109 (AM_HAL_PWRCTRL_MEMEN_SRAM_576K | \ 110 _VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_GROUP8)) 111 #define AM_HAL_PWRCTRL_MEMEN_SRAM_768K \ 112 (AM_HAL_PWRCTRL_MEMEN_SRAM_672K | \ 113 _VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_GROUP9)) 114 115 #define AM_HAL_PWRCTRL_MEMEN_SRAM_ALL (AM_HAL_PWRCTRL_MEMEN_SRAM_768K) 116 #define AM_HAL_PWRCTRL_MEMEN_FLASH_1M PWRCTRL_MEMPWREN_FLASH0_Msk 117 #define AM_HAL_PWRCTRL_MEMEN_FLASH_2M \ 118 (PWRCTRL_MEMPWREN_FLASH0_Msk | PWRCTRL_MEMPWREN_FLASH1_Msk) 119 #define AM_HAL_PWRCTRL_MEMEN_CACHE \ 120 (PWRCTRL_MEMPWREN_CACHEB0_Msk | PWRCTRL_MEMPWREN_CACHEB2_Msk) 121 #define AM_HAL_PWRCTRL_MEMEN_CACHE_DIS (~AM_HAL_PWRCTRL_MEMEN_CACHE) 122 123 // 124 //! Power up all available memory devices (this is the default power up state) 125 // 126 #define AM_HAL_PWRCTRL_MEMEN_ALL \ 127 (_VAL2FLD(PWRCTRL_MEMPWREN_DTCM, PWRCTRL_MEMPWREN_DTCM_ALL) | \ 128 _VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_ALL) | \ 129 _VAL2FLD(PWRCTRL_MEMPWREN_FLASH0, PWRCTRL_MEMPWREN_FLASH0_EN) | \ 130 _VAL2FLD(PWRCTRL_MEMPWREN_FLASH1, PWRCTRL_MEMPWREN_FLASH1_EN) | \ 131 _VAL2FLD(PWRCTRL_MEMPWREN_CACHEB0, PWRCTRL_MEMPWREN_CACHEB0_EN) | \ 132 _VAL2FLD(PWRCTRL_MEMPWREN_CACHEB2, PWRCTRL_MEMPWREN_CACHEB2_EN)) 133 134 //***************************************************************************** 135 // 136 //! Memory deepsleep powerdown values for all defined memory configurations. 137 // 138 //***************************************************************************** 139 #define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_8K_DTCM (_VAL2FLD(PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP, PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_GROUP0DTCM0)) 140 #define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_32K_DTCM (_VAL2FLD(PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP, PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_GROUP0)) 141 #define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_64K_DTCM (_VAL2FLD(PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP, PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_ALL)) 142 #define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_128K \ 143 (AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_64K_DTCM | \ 144 _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP0)) 145 #define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_192K \ 146 (AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_128K | \ 147 _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP1)) 148 #define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_256K \ 149 (AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_192K | \ 150 _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP2)) 151 #define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_320K \ 152 (AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_256K | \ 153 _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP3)) 154 #define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_384K \ 155 (AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_320K | \ 156 _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP4)) 157 #define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_448K \ 158 (AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_384K | \ 159 _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP5)) 160 #define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_512K \ 161 (AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_448K | \ 162 _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP6)) 163 #define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_576K \ 164 (AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_512K | \ 165 _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP7)) 166 #define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_672K \ 167 (AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_576K | \ 168 _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP8)) 169 #define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_768K \ 170 (AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_672K | \ 171 _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP9)) 172 173 #define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_ALL (AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_768K) 174 #define AM_HAL_PWRCTRL_MEMPWDINSLEEP_FLASH_1M PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP_Msk 175 #define AM_HAL_PWRCTRL_MEMPWDINSLEEP_FLASH_2M \ 176 (PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP_Msk | PWRCTRL_MEMPWDINSLEEP_FLASH1PWDSLP_Msk) 177 #define AM_HAL_PWRCTRL_MEMPWDINSLEEP_CACHE (PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP_Msk) 178 #define AM_HAL_PWRCTRL_MEMPWDINSLEEP_CACHE_DIS (~AM_HAL_PWRCTRL_MEMPWDINSLEEP_CACHE) 179 180 // 181 //! Power down all available memory devices 182 // 183 #define AM_HAL_PWRCTRL_MEMPWDINSLEEP_ALL \ 184 (_VAL2FLD(PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP, PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_ALL) | \ 185 _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_ALL) | \ 186 _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP, PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP_EN) | \ 187 _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_FLASH1PWDSLP, PWRCTRL_MEMPWDINSLEEP_FLASH1PWDSLP_EN) | \ 188 _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP, PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP_EN)) 189 190 //***************************************************************************** 191 // 192 //! Memory status values for all defined memory configurations 193 // 194 //***************************************************************************** 195 #define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_8K_DTCM \ 196 (PWRCTRL_MEMPWRSTATUS_DTCM00_Msk) 197 #define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_32K_DTCM \ 198 (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_8K_DTCM | \ 199 PWRCTRL_MEMPWRSTATUS_DTCM01_Msk) 200 #define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_64K_DTCM \ 201 (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_32K_DTCM | \ 202 PWRCTRL_MEMPWRSTATUS_DTCM1_Msk) 203 #define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_128K \ 204 (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_64K_DTCM | \ 205 PWRCTRL_MEMPWRSTATUS_SRAM0_Msk) 206 #define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_192K \ 207 (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_128K | \ 208 PWRCTRL_MEMPWRSTATUS_SRAM1_Msk) 209 #define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_256K \ 210 (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_192K | \ 211 PWRCTRL_MEMPWRSTATUS_SRAM2_Msk) 212 #define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_320K \ 213 (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_256K | \ 214 PWRCTRL_MEMPWRSTATUS_SRAM3_Msk) 215 #define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_384K \ 216 (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_320K | \ 217 PWRCTRL_MEMPWRSTATUS_SRAM4_Msk) 218 #define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_448K \ 219 (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_384K | \ 220 PWRCTRL_MEMPWRSTATUS_SRAM5_Msk) 221 #define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_512K \ 222 (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_448K | \ 223 PWRCTRL_MEMPWRSTATUS_SRAM6_Msk) 224 #define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_576K \ 225 (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_512K | \ 226 PWRCTRL_MEMPWRSTATUS_SRAM7_Msk) 227 #define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_672K \ 228 (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_576K | \ 229 PWRCTRL_MEMPWRSTATUS_SRAM8_Msk) 230 #define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_768K \ 231 (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_672K | \ 232 PWRCTRL_MEMPWRSTATUS_SRAM9_Msk) 233 #define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL \ 234 (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_768K) 235 #define AM_HAL_PWRCTRL_PWRONSTATUS_FLASH_1M \ 236 (PWRCTRL_MEMPWRSTATUS_FLASH0_Msk) 237 #define AM_HAL_PWRCTRL_PWRONSTATUS_FLASH_2M \ 238 (AM_HAL_PWRCTRL_PWRONSTATUS_FLASH_1M | \ 239 PWRCTRL_MEMPWRSTATUS_FLASH1_Msk) 240 #define AM_HAL_PWRCTRL_PWRONSTATUS_ALL \ 241 (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_768K | \ 242 AM_HAL_PWRCTRL_PWRONSTATUS_FLASH_2M) 243 244 //***************************************************************************** 245 // 246 //! Memory event values for all defined memory configurations 247 // 248 //***************************************************************************** 249 #define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_8K_DTCM \ 250 (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_DTCMEN, \ 251 PWRCTRL_MEMPWREVENTEN_DTCMEN_GROUP0DTCM0EN)) 252 #define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_32K_DTCM \ 253 (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_DTCMEN, \ 254 PWRCTRL_MEMPWREVENTEN_DTCMEN_GROUP0EN)) 255 #define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_64K_DTCM \ 256 (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_DTCMEN, \ 257 PWRCTRL_MEMPWREVENTEN_DTCMEN_ALL)) 258 #define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_128K \ 259 ((_VAL2FLD(PWRCTRL_MEMPWREVENTEN_DTCMEN, \ 260 PWRCTRL_MEMPWREVENTEN_DTCMEN_ALL)) | \ 261 (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_SRAMEN, \ 262 PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP0EN))) 263 #define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_192K \ 264 (AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_128K | \ 265 (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_SRAMEN, \ 266 PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP1EN))) 267 #define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_256K \ 268 (AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_192K | \ 269 (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_SRAMEN, \ 270 PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP2EN))) 271 #define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_320K \ 272 (AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_256K | \ 273 (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_SRAMEN, \ 274 PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP3EN))) 275 #define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_384K \ 276 (AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_320K | \ 277 (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_SRAMEN, \ 278 PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP4EN))) 279 #define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_448K \ 280 (AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_384K | \ 281 (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_SRAMEN, \ 282 PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP5EN))) 283 #define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_512K \ 284 (AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_448K | \ 285 (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_SRAMEN, \ 286 PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP6EN))) 287 #define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_576K \ 288 (AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_512K | \ 289 (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_SRAMEN, \ 290 PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP7EN))) 291 #define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_672K \ 292 (AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_576K | \ 293 (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_SRAMEN, \ 294 PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP8EN))) 295 #define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_768K \ 296 (AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_672K | \ 297 (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_SRAMEN, \ 298 PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP9EN))) 299 #define AM_HAL_PWRCTRL_MEMPWREVENTEN_FLASH_1M \ 300 (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_FLASH0EN, \ 301 PWRCTRL_MEMPWREVENTEN_FLASH0EN_EN)) 302 #define AM_HAL_PWRCTRL_MEMPWREVENTEN_FLASH_2M \ 303 (AM_HAL_PWRCTRL_MEMPWREVENTEN_FLASH_1M | \ 304 (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_FLASH1EN, \ 305 PWRCTRL_MEMPWREVENTEN_FLASH1EN_EN))) 306 #define AM_HAL_PWRCTRL_MEMPWREVENTEN_CACHE \ 307 ((_VAL2FLD(PWRCTRL_MEMPWREVENTEN_CACHEB0EN, \ 308 PWRCTRL_MEMPWREVENTEN_CACHEB0EN_EN)) | \ 309 (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_CACHEB2EN, \ 310 PWRCTRL_MEMPWREVENTEN_CACHEB2EN_EN))) 311 #define AM_HAL_PWRCTRL_MEMPWREVENTEN_ALL \ 312 (AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_768K | \ 313 AM_HAL_PWRCTRL_MEMPWREVENTEN_FLASH_2M | \ 314 AM_HAL_PWRCTRL_MEMPWREVENTEN_CACHE) 315 316 //***************************************************************************** 317 // 318 //! Memory region mask values for all defined memory configurations 319 // 320 //***************************************************************************** 321 #define AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK AM_HAL_PWRCTRL_MEMEN_SRAM_ALL 322 #define AM_HAL_PWRCTRL_MEM_REGION_FLASH_MASK AM_HAL_PWRCTRL_MEMEN_FLASH_2M 323 #define AM_HAL_PWRCTRL_MEM_REGION_CACHE_MASK AM_HAL_PWRCTRL_MEMEN_CACHE 324 #define AM_HAL_PWRCTRL_MEM_REGION_ALT_CACHE_MASK AM_HAL_PWRCTRL_PWRONSTATUS_CACHE 325 #define AM_HAL_PWRCTRL_MEM_REGION_ALL_MASK AM_HAL_PWRCTRL_MEMEN_ALL 326 #define AM_HAL_PWRCTRL_MEM_REGION_ALT_ALL_MASK AM_HAL_PWRCTRL_PWRONSTATUS_ALL 327 328 #endif // AM_HAL_PWRCTRL_INTERNAL_H 329 330 //***************************************************************************** 331 // 332 // End Doxygen group. 333 //! @} 334 // 335 //***************************************************************************** 336
