1 //*****************************************************************************
2 //
3 //! @file am_hal_mpu.c
4 //!
5 //! @brief Hardware abstraction for the Memory Protection Unit.
6 //!
7 //! @addtogroup mpu_4p MPU - Memory Protection Unit
8 //! @ingroup apollo4p_hal
9 //! @{
10 //
11 //*****************************************************************************
12
13 //*****************************************************************************
14 //
15 // Copyright (c) 2023, Ambiq Micro, Inc.
16 // All rights reserved.
17 //
18 // Redistribution and use in source and binary forms, with or without
19 // modification, are permitted provided that the following conditions are met:
20 //
21 // 1. Redistributions of source code must retain the above copyright notice,
22 // this list of conditions and the following disclaimer.
23 //
24 // 2. Redistributions in binary form must reproduce the above copyright
25 // notice, this list of conditions and the following disclaimer in the
26 // documentation and/or other materials provided with the distribution.
27 //
28 // 3. Neither the name of the copyright holder nor the names of its
29 // contributors may be used to endorse or promote products derived from this
30 // software without specific prior written permission.
31 //
32 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
33 // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
34 // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
35 // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
36 // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
37 // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
38 // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
39 // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
40 // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
41 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
42 // POSSIBILITY OF SUCH DAMAGE.
43 //
44 // This is part of revision release_sdk_4_4_0-3c5977e664 of the AmbiqSuite Development Package.
45 //
46 //*****************************************************************************
47
48 #include "am_hal_mpu.h"
49
50 //*****************************************************************************
51 //
52 // Returns the contents of the MPU_TYPE register
53 //
54 //*****************************************************************************
55 uint32_t
am_hal_mpu_type_get(uint32_t * pui32Type)56 am_hal_mpu_type_get(uint32_t *pui32Type)
57 {
58 *pui32Type = MPU->TYPE ;
59
60 return AM_HAL_STATUS_SUCCESS;
61 }
62
63 //*****************************************************************************
64 //
65 // Sets the global configuration of the MPU
66 //
67 //*****************************************************************************
68 uint32_t
am_hal_mpu_global_configure(bool bMPUEnable,bool bPrivilegedDefault,bool bFaultNMIProtect)69 am_hal_mpu_global_configure(bool bMPUEnable,
70 bool bPrivilegedDefault,
71 bool bFaultNMIProtect)
72 {
73 __DMB();
74
75 MPU->CTRL = _VAL2FLD(MPU_CTRL_ENABLE, (uint32_t)bMPUEnable ) |
76 _VAL2FLD(MPU_CTRL_HFNMIENA, (uint32_t)bFaultNMIProtect ) |
77 _VAL2FLD(MPU_CTRL_PRIVDEFENA, (uint32_t)bPrivilegedDefault ) ;
78
79
80 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
81
82 __DSB();
83 __ISB();
84
85 return AM_HAL_STATUS_SUCCESS;
86 }
87
88 //*****************************************************************************
89 //
90 // Configures an MPU region.
91 //
92 //*****************************************************************************
93 uint32_t
am_hal_mpu_region_configure(tMPURegion * psConfig,bool bEnableNow)94 am_hal_mpu_region_configure(tMPURegion *psConfig, bool bEnableNow)
95 {
96
97 #ifndef AM_HAL_DISABLE_API_VALIDATION
98
99 if (psConfig->ui8RegionNumber > _FLD2VAL( MPU_RBAR_REGION , 0xFFFFFFFF ) ) //(MPU_RBAR_REGION_Msk >>MPU_RBAR_REGION_Pos) )
100 {
101 return AM_HAL_STATUS_INVALID_ARG;
102 }
103 if (psConfig->eAccessPermission > _FLD2VAL( MPU_RASR_AP, 0xFFFFFFFF)) // (MPU_RASR_AP_Msk >> MPU_RASR_AP_Pos))
104 {
105 return AM_HAL_STATUS_INVALID_ARG;
106 }
107 if (psConfig->ui16SubRegionDisable > _FLD2VAL(MPU_RASR_SRD, 0xFFFFFFFF)) // (MPU_RASR_SRD_Msk >> MPU_RASR_SRD_Pos))
108 {
109 return AM_HAL_STATUS_INVALID_ARG;
110 }
111 if (psConfig->ui8Size > _FLD2VAL(MPU_RASR_SIZE, 0xFFFFFFFF)) // (MPU_RASR_SIZE_Msk >> MPU_RASR_SIZE_Pos))
112 {
113 return AM_HAL_STATUS_INVALID_ARG;
114 }
115
116 #endif // AM_HAL_DISABLE_API_VALIDATION
117
118 //
119 // Set the new base address for the specified region.
120 //
121 MPU->RBAR = (psConfig->ui32BaseAddress & MPU_RBAR_ADDR_Msk) |
122 _VAL2FLD(MPU_RBAR_REGION, psConfig->ui8RegionNumber ) |
123 _VAL2FLD(MPU_RBAR_VALID, 1 ) ;
124
125 //
126 // Set the attributes for this region based on the input structure.
127 //
128 MPU->RASR = _VAL2FLD(MPU_RASR_XN, (uint32_t) psConfig->bExecuteNever ) |
129 _VAL2FLD(MPU_RASR_AP, psConfig->eAccessPermission) |
130 _VAL2FLD(MPU_RASR_SRD, psConfig->ui16SubRegionDisable) |
131 _VAL2FLD(MPU_RASR_SIZE, psConfig->ui8Size ) |
132 _VAL2FLD(MPU_RASR_ENABLE, (uint32_t) bEnableNow ) |
133 MPU_DEFAULT_TEXSCB;
134
135 return AM_HAL_STATUS_SUCCESS;
136 }
137
138 //*****************************************************************************
139 //
140 // Enable an MPU region.
141 //
142 //*****************************************************************************
143 uint32_t
am_hal_mpu_region_enable(uint8_t ui8RegionNumber)144 am_hal_mpu_region_enable(uint8_t ui8RegionNumber)
145 {
146 #ifndef AM_HAL_DISABLE_API_VALIDATION
147 if (ui8RegionNumber > _FLD2VAL(MPU_RBAR_REGION, 0xFFFFFFFF))
148 {
149 return AM_HAL_STATUS_INVALID_ARG;
150 }
151 #endif
152 //
153 // Set the region number in the MPU_RNR register, and set the enable bit.
154 //
155
156 MPU->RNR = _VAL2FLD(MPU_RBAR_REGION, ui8RegionNumber);
157 MPU->RASR |= MPU_RASR_ENABLE_Msk;
158
159 return AM_HAL_STATUS_SUCCESS;
160 }
161
162 //*****************************************************************************
163 //
164 // Disable an MPU region.
165 //
166 //*****************************************************************************
167 uint32_t
am_hal_mpu_region_disable(uint8_t ui8RegionNumber)168 am_hal_mpu_region_disable(uint8_t ui8RegionNumber)
169 {
170 #ifndef AM_HAL_DISABLE_API_VALIDATION
171 if (ui8RegionNumber > _FLD2VAL(MPU_RBAR_REGION, 0xFFFFFFFF))
172 {
173 return AM_HAL_STATUS_INVALID_ARG;
174 }
175 #endif
176 //
177 // Set the region number in the MPU_RNR register, and clear the enable bit.
178 //
179 MPU->RNR = _VAL2FLD(MPU_RBAR_REGION, ui8RegionNumber);
180 MPU->RASR &= ~(MPU_RASR_ENABLE_Msk);
181
182 return AM_HAL_STATUS_SUCCESS;
183 }
184
185 //*****************************************************************************
186 //
187 // Get the MPU region number.
188 //
189 //*****************************************************************************
190 uint32_t
am_hal_mpu_get_region_number(uint32_t * ui32pMpuRNR)191 am_hal_mpu_get_region_number(uint32_t *ui32pMpuRNR)
192 {
193 *ui32pMpuRNR = _FLD2VAL( MPU_RBAR_REGION, MPU->RNR);
194
195 return AM_HAL_STATUS_SUCCESS;
196 }
197
198 //*****************************************************************************
199 //
200 // End Doxygen group.
201 //! @}
202 //
203 //*****************************************************************************
204
205
