1 //***************************************************************************** 2 // 3 //! @file am_hal_mcu_sysctrl.h 4 //! 5 //! @brief Functions for interfacing with the M4F system control registers 6 //! 7 //! @addtogroup sysctrl4_4p SYSCTRL - System Control 8 //! @ingroup apollo4p_hal 9 //! @{ 10 // 11 //***************************************************************************** 12 13 //***************************************************************************** 14 // 15 // Copyright (c) 2023, Ambiq Micro, Inc. 16 // All rights reserved. 17 // 18 // Redistribution and use in source and binary forms, with or without 19 // modification, are permitted provided that the following conditions are met: 20 // 21 // 1. Redistributions of source code must retain the above copyright notice, 22 // this list of conditions and the following disclaimer. 23 // 24 // 2. Redistributions in binary form must reproduce the above copyright 25 // notice, this list of conditions and the following disclaimer in the 26 // documentation and/or other materials provided with the distribution. 27 // 28 // 3. Neither the name of the copyright holder nor the names of its 29 // contributors may be used to endorse or promote products derived from this 30 // software without specific prior written permission. 31 // 32 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 33 // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 36 // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 37 // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 38 // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 39 // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 40 // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 41 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 42 // POSSIBILITY OF SUCH DAMAGE. 43 // 44 // This is part of revision release_sdk_4_4_0-3c5977e664 of the AmbiqSuite Development Package. 45 // 46 //***************************************************************************** 47 #ifndef AM_HAL_MCU_SYSCTRL_H 48 #define AM_HAL_MCU_SYSCTRL_H 49 50 #ifdef __cplusplus 51 extern "C" 52 { 53 #endif 54 55 //***************************************************************************** 56 // 57 //! Write flush - This function will hold the bus until all queued write 58 //! operations have completed, thereby guaranteeing that all writes have 59 //! been flushed. 60 // 61 //***************************************************************************** 62 #define am_hal_sysctrl_membarrier() \ 63 if (1) \ 64 { \ 65 __DMB(); \ 66 am_hal_sysctrl_bus_write_flush(); \ 67 } 68 69 // 70 //! This Write will begin only after all previous load/store operations are done 71 // 72 #define am_hal_sysctrl_membarrier_write(addr, data) \ 73 if (1) \ 74 { \ 75 am_hal_sysctrl_membarrier(); \ 76 *((uint32_t *)(addr)) = (data); \ 77 } 78 79 // 80 //! This Read will be performed before any subsequent load/store operations are done 81 // 82 #define am_hal_sysctrl_membarrier_read(addr) \ 83 if (1) \ 84 { \ 85 AM_REGVAL((addr)); \ 86 am_hal_sysctrl_membarrier(); \ 87 } 88 89 //***************************************************************************** 90 // 91 // External function definitions 92 // 93 //***************************************************************************** 94 95 //***************************************************************************** 96 // 97 //! @brief Enable the floating point module. 98 //! 99 //! Call this function to enable the ARM hardware floating point module. 100 // 101 //***************************************************************************** 102 extern void am_hal_sysctrl_fpu_enable(void); 103 104 //***************************************************************************** 105 // 106 //! @brief Disable the floating point module. 107 //! 108 //! Call this function to disable the ARM hardware floating point module. 109 // 110 //***************************************************************************** 111 extern void am_hal_sysctrl_fpu_disable(void); 112 113 //***************************************************************************** 114 // 115 //! @brief Enable stacking of FPU registers on exception entry. 116 //! 117 //! @param bLazy - Set to "true" to enable "lazy stacking". 118 //! 119 //! This function allows the core to save floating-point information to the 120 //! stack on exception entry. Setting the bLazy option enables "lazy stacking" 121 //! for interrupt handlers. Normally, mixing floating-point code and interrupt 122 //! driven routines causes increased interrupt latency, because the core must 123 //! save extra information to the stack upon exception entry. With the lazy 124 //! stacking option enabled, the core will skip the saving of floating-point 125 //! registers when possible, reducing average interrupt latency. 126 //! 127 //! @note At reset of the Cortex M4, the ASPEN and LSPEN bits are set to 1, 128 //! enabling Lazy mode by default. Therefore this function will generally 129 //! only have an affect when setting for full-context save (or when switching 130 //! from full-context to lazy mode). 131 //! 132 //! @note See also: 133 //! infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0298a/DAFGGBJD.html 134 //! 135 //! @note Three valid FPU context saving modes are possible. 136 //! 1. Lazy ASPEN=1 LSPEN=1 am_hal_sysctrl_fpu_stacking_enable(true) 137 //! and default. 138 //! 2. Full-context ASPEN=1 LSPEN=0 am_hal_sysctrl_fpu_stacking_enable(false) 139 //! 3. No FPU state ASPEN=0 LSPEN=0 am_hal_sysctrl_fpu_stacking_disable() 140 //! 4. Invalid ASPEN=0 LSPEN=1 141 // 142 //***************************************************************************** 143 extern void am_hal_sysctrl_fpu_stacking_enable(bool bLazy); 144 145 //***************************************************************************** 146 // 147 //! @brief Disable FPU register stacking on exception entry. 148 //! 149 //! This function disables all stacking of floating point registers for 150 //! interrupt handlers. This mode should only be used when it is absolutely 151 //! known that no FPU instructions will be executed in an ISR. 152 // 153 //***************************************************************************** 154 extern void am_hal_sysctrl_fpu_stacking_disable(void); 155 156 //***************************************************************************** 157 // 158 //! @brief Issue a system wide reset using the AIRCR bit in the M4 system ctrl. 159 //! 160 //! This function issues a system wide reset (Apollo4P POR level reset). 161 // 162 //***************************************************************************** 163 extern void am_hal_sysctrl_aircr_reset(void); 164 #ifdef __cplusplus 165 } 166 #endif 167 168 #endif // AM_HAL_MCU_SYSCTRL_H 169 170 //***************************************************************************** 171 // 172 // End Doxygen group. 173 //! @} 174 // 175 //***************************************************************************** 176 177
