1/*
2 * Copyright (c) 2023-2024 Analog Devices, Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm/armv7-m.dtsi>
8#include <adi/max32/max32xxx.dtsi>
9#include <zephyr/dt-bindings/dma/max32690_dma.h>
10
11&clk_ipo {
12	clock-frequency = <DT_FREQ_M(120)>;
13};
14
15&sram0 {
16	reg = <0x20000000 DT_SIZE_K(128)>;
17};
18
19&flash0 {
20	reg = <0x10000000 DT_SIZE_M(3)>;
21	erase-block-size = <16384>;
22};
23
24&pinctrl {
25	reg = <0x40008000 0x3220>;
26
27	gpio2: gpio@4000a000 {
28		reg = <0x4000a000 0x1000>;
29		compatible = "adi,max32-gpio";
30		gpio-controller;
31		#gpio-cells = <2>;
32		interrupts = <26 0>;
33		clocks = <&gcr ADI_MAX32_CLOCK_BUS0 2>;
34		status = "disabled";
35	};
36
37	gpio3: gpio@40080400 {
38		reg = <0x40080400 0x200>;
39		compatible = "adi,max32-gpio";
40		gpio-controller;
41		#gpio-cells = <2>;
42		interrupts = <58 0>;
43		clocks = <&gcr ADI_MAX32_CLOCK_BUS2 0>;
44		status = "disabled";
45	};
46
47	gpio4: gpio@4000c000 {
48		reg = <0x4000c000 0x20>;
49		compatible = "adi,max32-gpio";
50		gpio-controller;
51		#gpio-cells = <2>;
52		interrupts = <54 0>;
53		status = "disabled";
54	};
55};
56
57&adc {
58	compatible = "adi,max32-adc-sar", "adi,max32-adc";
59	clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
60	clock-divider = <16>;
61	channel-count = <21>;
62	track-count = <4>;
63	idle-count = <5>;
64	vref-mv = <1250>;
65	resolution = <12>;
66};
67
68/* MAX32690 extra peripherals. */
69/ {
70	soc {
71		sram1: memory@20020000 {
72			compatible = "mmio-sram";
73			reg = <0x20020000 DT_SIZE_K(128)>;
74		};
75
76		sram2: memory@20040000 {
77			compatible = "mmio-sram";
78			reg = <0x20040000 DT_SIZE_K(128)>;
79		};
80
81		sram3: memory@20060000 {
82			compatible = "mmio-sram";
83			reg = <0x20060000 DT_SIZE_K(128)>;
84		};
85
86		sram4: memory@20080000 {
87			compatible = "mmio-sram";
88			reg = <0x20080000 DT_SIZE_K(128)>;
89		};
90
91		sram5: memory@200a0000 {
92			compatible = "mmio-sram";
93			reg = <0x200a0000 DT_SIZE_K(128)>;
94		};
95
96		sram6: memory@200c0000 {
97			compatible = "mmio-sram";
98			reg = <0x200c0000 DT_SIZE_K(64)>;
99		};
100
101		sram7: memory@200d0000 {
102			compatible = "mmio-sram";
103			reg = <0x200d0000 DT_SIZE_K(64)>;
104		};
105
106		flc1: flash_controller@40029400 {
107			compatible = "adi,max32-flash-controller";
108			reg = <0x40029400 0x400>;
109
110			#address-cells = <1>;
111			#size-cells = <1>;
112			status = "okay";
113
114			flash1: flash@10080000 {
115				compatible = "soc-nv-flash";
116				reg = <0x10080000 DT_SIZE_K(256)>;
117				write-block-size = <16>;
118				erase-block-size = <16384>;
119			};
120		};
121
122		spi0: spi@40046000 {
123			compatible = "adi,max32-spi";
124			reg = <0x40046000 0x1000>;
125			#address-cells = <1>;
126			#size-cells = <0>;
127			clocks = <&gcr ADI_MAX32_CLOCK_BUS0 6>;
128			interrupts = <16 0>;
129			status = "disabled";
130		};
131
132		spi1: spi@40047000 {
133			compatible = "adi,max32-spi";
134			reg = <0x40047000 0x1000>;
135			#address-cells = <1>;
136			#size-cells = <0>;
137			clocks = <&gcr ADI_MAX32_CLOCK_BUS0 7>;
138			interrupts = <17 0>;
139			status = "disabled";
140		};
141
142		spi2: spi@40048000 {
143			compatible = "adi,max32-spi";
144			reg = <0x40048000 0x1000>;
145			#address-cells = <1>;
146			#size-cells = <0>;
147			clocks = <&gcr ADI_MAX32_CLOCK_BUS0 8>;
148			interrupts = <18 0>;
149			status = "disabled";
150		};
151
152		spi3: spi@400be000 {
153			compatible = "adi,max32-spi";
154			reg = <0x400be000 0x400>;
155			#address-cells = <1>;
156			#size-cells = <0>;
157			clocks = <&gcr ADI_MAX32_CLOCK_BUS1 16>;
158			interrupts = <56 0>;
159			status = "disabled";
160		};
161
162		spi4: spi@400be400 {
163			compatible = "adi,max32-spi";
164			reg = <0x400be400 0x400>;
165			#address-cells = <1>;
166			#size-cells = <0>;
167			clocks = <&gcr ADI_MAX32_CLOCK_BUS1 17>;
168			interrupts = <105 0>;
169			status = "disabled";
170		};
171
172		uart3: serial@40081400 {
173			compatible = "adi,max32-uart";
174			reg = <0x40081400 0x400>;
175			clocks = <&gcr ADI_MAX32_CLOCK_BUS2 4>;
176			clock-source = <ADI_MAX32_PRPH_CLK_SRC_IBRO>;
177			interrupts = <88 0>;
178			status = "disabled";
179		};
180
181		dma0: dma@40028000 {
182			compatible = "adi,max32-dma";
183			reg = <0x40028000 0x1000>;
184			clocks = <&gcr ADI_MAX32_CLOCK_BUS0 5>;
185			interrupts = <28 0>, <29 0>, <30 0>, <31 0>;
186			dma-channels = <16>;
187			status = "disabled";
188			#dma-cells = <2>;
189		};
190
191		wdt1: watchdog@40080800  {
192			compatible = "adi,max32-watchdog";
193			reg = <0x40080800 0x400>;
194			interrupts = <57 0>;
195			clocks = <&gcr ADI_MAX32_CLOCK_BUS2 1>;
196			clock-source = <ADI_MAX32_PRPH_CLK_SRC_IBRO>;
197			status = "disabled";
198		};
199
200		lptimer0: timer@40080c00 {
201			compatible = "adi,max32-timer";
202			reg = <0x40080c00 0x400>;
203			interrupts = <9 0>;
204			status = "disabled";
205			clocks = <&gcr ADI_MAX32_CLOCK_BUS2 2>;
206			clock-source = <ADI_MAX32_PRPH_CLK_SRC_IBRO>;
207			prescaler = <1>;
208			counter {
209				compatible = "adi,max32-counter";
210				status = "disabled";
211			};
212		};
213
214		lptimer1: timer@40081000 {
215			compatible = "adi,max32-timer";
216			reg = <0x40081000 0x400>;
217			interrupts = <10 0>;
218			status = "disabled";
219			clocks = <&gcr ADI_MAX32_CLOCK_BUS2 3>;
220			clock-source = <ADI_MAX32_PRPH_CLK_SRC_IBRO>;
221			prescaler = <1>;
222			counter {
223				compatible = "adi,max32-counter";
224				status = "disabled";
225			};
226		};
227
228		w1: w1@4003d000 {
229			compatible = "adi,max32-w1";
230			reg = <0x4003d000 0x1000>;
231			clocks = <&gcr ADI_MAX32_CLOCK_BUS1 13>;
232			interrupts = <67 0>;
233			status = "disabled";
234		};
235	};
236};
237