1/*
2 * Copyright (c) 2024 Analog Devices, Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm/armv7-m.dtsi>
8#include <adi/max32/max32xxx.dtsi>
9
10&sram0 {
11	reg = <0x20000000 DT_SIZE_K(16)>;
12};
13
14&clk_inro {
15	clock-frequency = <DT_FREQ_K(80)>;
16};
17
18&i2c2 {
19	clocks = <&gcr ADI_MAX32_CLOCK_BUS1 21>;
20};
21
22/delete-node/ &clk_iso;
23
24/* MAX32672 extra peripherals. */
25/ {
26	soc {
27		sram1: memory@20004000 {
28			compatible = "mmio-sram";
29			reg = <0x20004000 DT_SIZE_K(16)>;
30		};
31
32		sram2: memory@20008000 {
33			compatible = "mmio-sram";
34			reg = <0x20008000 DT_SIZE_K(64)>;
35		};
36
37		sram3: memory@20018000 {
38			compatible = "mmio-sram";
39			reg = <0x20018000 DT_SIZE_K(64)>;
40		};
41
42		sram4: memory@20028000 {
43			compatible = "mmio-sram";
44			reg = <0x20028000 DT_SIZE_K(4)>;
45		};
46
47		sram5: memory@20029000 {
48			compatible = "mmio-sram";
49			reg = <0x20029000 DT_SIZE_K(4)>;
50		};
51
52		sram6: memory@2002a000 {
53			compatible = "mmio-sram";
54			reg = <0x2002a000 DT_SIZE_K(16)>;
55		};
56
57		sram7: memory@2002e000 {
58			compatible = "mmio-sram";
59			reg = <0x2002e000 DT_SIZE_K(16)>;
60		};
61
62		flc1: flash_controller@40029400 {
63			compatible = "adi,max32-flash-controller";
64			reg = <0x40029400 0x400>;
65
66			#address-cells = <1>;
67			#size-cells = <1>;
68			status = "okay";
69
70			flash1: flash@10080000 {
71				compatible = "soc-nv-flash";
72				reg = <0x10080000 DT_SIZE_K(512)>;
73				write-block-size = <16>;
74				erase-block-size = <8192>;
75			};
76		};
77
78		uart3: serial@40145000 {
79			compatible = "adi,max32-uart";
80			reg = <0x40145000 0x1000>;
81			clocks = <&gcr ADI_MAX32_CLOCK_BUS2 2>;
82			clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
83			interrupts = <88 0>;
84			status = "disabled";
85		};
86	};
87};
88