1/*
2 * Copyright (c) 2023-2024 Analog Devices, Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm/armv7-m.dtsi>
8#include <adi/max32/max32xxx.dtsi>
9
10&pinctrl {
11	reg = <0x40008000 0x2400>;
12
13	gpio2: gpio@40080400 {
14		reg = <0x40080400 0x200>;
15		compatible = "adi,max32-gpio";
16		gpio-controller;
17		#gpio-cells = <2>;
18		interrupts = <26 0>;
19		clocks = <&gcr ADI_MAX32_CLOCK_BUS2 0>;
20		status = "disabled";
21	};
22
23	gpio3: gpio@40080600 {
24		reg = <0x40080600 0x200>;
25		compatible = "adi,max32-gpio";
26		gpio-controller;
27		#gpio-cells = <2>;
28		interrupts = <54 0>;
29		status = "disabled";
30	};
31};
32
33/* MAX32655 extra peripherals. */
34/ {
35	soc {
36		sram1: memory@20008000 {
37			compatible = "mmio-sram";
38			reg = <0x20008000 DT_SIZE_K(32)>;
39		};
40
41		sram2: memory@20010000 {
42			compatible = "mmio-sram";
43			reg = <0x20010000 DT_SIZE_K(48)>;
44		};
45
46		sram3: memory@2001c000 {
47			compatible = "mmio-sram";
48			reg = <0x2001c000 DT_SIZE_K(16)>;
49		};
50
51		uart3: serial@40081400 {
52			compatible = "adi,max32-uart";
53			reg = <0x40081400 0x1000>;
54			clocks = <&gcr ADI_MAX32_CLOCK_BUS2 4>;
55			clock-source = <ADI_MAX32_PRPH_CLK_SRC_IBRO>;
56			interrupts = <88 0>;
57			status = "disabled";
58		};
59
60		dma0: dma@40028000 {
61			compatible = "adi,max32-dma";
62			reg = <0x40028000 0x1000>;
63			clocks = <&gcr ADI_MAX32_CLOCK_BUS0 5>;
64			interrupts = <28 0>, <29 0>, <30 0>, <31 0>;
65			dma-channels = <4>;
66			status = "disabled";
67			#dma-cells = <2>;
68		};
69
70		wdt1: watchdog@40080800  {
71			compatible = "adi,max32-watchdog";
72			reg = <0x40080800 0x400>;
73			interrupts = <57 0>;
74			clocks = <&gcr ADI_MAX32_CLOCK_BUS2 1>;
75			clock-source = <ADI_MAX32_PRPH_CLK_SRC_IBRO>;
76			status = "disabled";
77		};
78
79		spi0: spi@400be000 {
80			compatible = "adi,max32-spi";
81			reg = <0x400be000 0x1000>;
82			#address-cells = <1>;
83			#size-cells = <0>;
84			clocks = <&gcr ADI_MAX32_CLOCK_BUS1 16>;
85			interrupts = <56 0>;
86			status = "disabled";
87		};
88
89		spi1: spi@40046000 {
90			compatible = "adi,max32-spi";
91			reg = <0x40046000 0x1000>;
92			#address-cells = <1>;
93			#size-cells = <0>;
94			clocks = <&gcr ADI_MAX32_CLOCK_BUS0 6>;
95			interrupts = <16 0>;
96			status = "disabled";
97		};
98
99		lptimer0: timer@40080c00 {
100			compatible = "adi,max32-timer";
101			reg = <0x40080c00 0x400>;
102			interrupts = <9 0>;
103			status = "disabled";
104			clocks = <&gcr ADI_MAX32_CLOCK_BUS2 2>;
105			clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
106			prescaler = <1>;
107			counter {
108				compatible = "adi,max32-counter";
109				status = "disabled";
110			};
111		};
112
113		lptimer1: timer@40081000 {
114			compatible = "adi,max32-timer";
115			reg = <0x40081000 0x400>;
116			interrupts = <10 0>;
117			status = "disabled";
118			clocks = <&gcr ADI_MAX32_CLOCK_BUS2 3>;
119			clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
120			prescaler = <1>;
121			counter {
122				compatible = "adi,max32-counter";
123				status = "disabled";
124			};
125		};
126
127		w1: w1@4003d000 {
128			compatible = "adi,max32-w1";
129			reg = <0x4003d000 0x1000>;
130			clocks = <&gcr ADI_MAX32_CLOCK_BUS1 13>;
131			interrupts = <67 0>;
132			status = "disabled";
133		};
134	};
135};
136