1 /*
2 * Copyright (c) 2017-2018, 2020, NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT nxp_kinetis_adc16
8
9 #include <errno.h>
10 #include <zephyr/drivers/adc.h>
11 #include <zephyr/drivers/pinctrl.h>
12 #ifdef CONFIG_ADC_MCUX_ADC16_ENABLE_EDMA
13 #include <zephyr/drivers/dma.h>
14 #endif
15
16 #include <fsl_adc16.h>
17
18 #define LOG_LEVEL CONFIG_ADC_LOG_LEVEL
19 #include <zephyr/logging/log.h>
20 #include <zephyr/irq.h>
21 LOG_MODULE_REGISTER(adc_mcux_adc16);
22
23 #define ADC_CONTEXT_USES_KERNEL_TIMER
24 #include "adc_context.h"
25
26 struct mcux_adc16_config {
27 ADC_Type *base;
28 #ifndef CONFIG_ADC_MCUX_ADC16_ENABLE_EDMA
29 void (*irq_config_func)(const struct device *dev);
30 #endif
31 uint32_t clk_source; /* ADC clock source selection */
32 uint32_t long_sample; /* ADC long sample mode selection */
33 uint32_t hw_trigger_src; /* ADC hardware trigger source */
34 /* defined in SIM module SOPT7 */
35 #ifdef CONFIG_ADC_MCUX_ADC16_ENABLE_EDMA
36 uint32_t dma_slot; /* ADC DMA MUX slot */
37 #endif
38 uint32_t trg_offset;
39 uint32_t trg_bits;
40 uint32_t alt_offset;
41 uint32_t alt_bits;
42 bool periodic_trigger; /* ADC enable periodic trigger */
43 bool channel_mux_b;
44 bool high_speed; /* ADC enable high speed mode*/
45 bool continuous_convert; /* ADC enable continuous convert*/
46 const struct pinctrl_dev_config *pincfg;
47 };
48
49 #ifdef CONFIG_ADC_MCUX_ADC16_ENABLE_EDMA
50 struct adc_edma_config {
51 int32_t state;
52 uint32_t dma_channel;
53 void (*irq_call_back)(void);
54 struct dma_config dma_cfg;
55 struct dma_block_config dma_block;
56 };
57 #endif
58
59 struct mcux_adc16_data {
60 const struct device *dev;
61 struct adc_context ctx;
62 #ifdef CONFIG_ADC_MCUX_ADC16_ENABLE_EDMA
63 const struct device *dev_dma;
64 struct adc_edma_config adc_dma_config;
65 #endif
66 uint16_t *buffer;
67 uint16_t *repeat_buffer;
68 uint32_t channels;
69 uint8_t channel_id;
70 };
71
72 #ifdef CONFIG_ADC_MCUX_ADC16_HW_TRIGGER
73 #define SIM_SOPT7_ADCSET(x, shifts, mask) \
74 (((uint32_t)(((uint32_t)(x)) << shifts)) & mask)
75 #endif
76
77 #ifdef CONFIG_ADC_MCUX_ADC16_ENABLE_EDMA
adc_dma_callback(const struct device * dma_dev,void * callback_arg,uint32_t channel,int status)78 static void adc_dma_callback(const struct device *dma_dev, void *callback_arg,
79 uint32_t channel, int status)
80 {
81 const struct device *dev = (const struct device *)callback_arg;
82 struct mcux_adc16_data *data = dev->data;
83
84 LOG_DBG("DMA done");
85 data->buffer++;
86 adc_context_on_sampling_done(&data->ctx, dev);
87 }
88 #endif
89
90 #ifdef CONFIG_ADC_MCUX_ADC16_HW_TRIGGER
adc_hw_trigger_enable(const struct device * dev)91 static void adc_hw_trigger_enable(const struct device *dev)
92 {
93 const struct mcux_adc16_config *config = dev->config;
94
95 /* enable ADC trigger channel */
96 SIM->SOPT7 |= SIM_SOPT7_ADCSET(config->hw_trigger_src,
97 config->trg_offset, config->trg_bits) |
98 SIM_SOPT7_ADCSET(1, config->alt_offset, config->alt_bits);
99 }
100 #endif
101
mcux_adc16_channel_setup(const struct device * dev,const struct adc_channel_cfg * channel_cfg)102 static int mcux_adc16_channel_setup(const struct device *dev,
103 const struct adc_channel_cfg *channel_cfg)
104 {
105 uint8_t channel_id = channel_cfg->channel_id;
106
107 if (channel_id > (ADC_SC1_ADCH_MASK >> ADC_SC1_ADCH_SHIFT)) {
108 LOG_ERR("Channel %d is not valid", channel_id);
109 return -EINVAL;
110 }
111
112 if (channel_cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT) {
113 LOG_ERR("Invalid channel acquisition time");
114 return -EINVAL;
115 }
116
117 if (channel_cfg->differential) {
118 LOG_ERR("Differential channels are not supported");
119 return -EINVAL;
120 }
121
122 if (channel_cfg->gain != ADC_GAIN_1) {
123 LOG_ERR("Invalid channel gain");
124 return -EINVAL;
125 }
126
127 #ifdef CONFIG_ADC_MCUX_ADC16_HW_TRIGGER
128 adc_hw_trigger_enable(dev);
129 #endif
130
131 return 0;
132 }
133
start_read(const struct device * dev,const struct adc_sequence * sequence)134 static int start_read(const struct device *dev,
135 const struct adc_sequence *sequence)
136 {
137 const struct mcux_adc16_config *config = dev->config;
138 struct mcux_adc16_data *data = dev->data;
139 adc16_hardware_average_mode_t mode;
140 adc16_resolution_t resolution;
141 int error;
142 uint32_t tmp32;
143 ADC_Type *base = config->base;
144
145 switch (sequence->resolution) {
146 case 8:
147 case 9:
148 resolution = kADC16_Resolution8or9Bit;
149 break;
150 case 10:
151 case 11:
152 resolution = kADC16_Resolution10or11Bit;
153 break;
154 case 12:
155 case 13:
156 resolution = kADC16_Resolution12or13Bit;
157 break;
158 #if defined(FSL_FEATURE_ADC16_MAX_RESOLUTION) && \
159 (FSL_FEATURE_ADC16_MAX_RESOLUTION >= 16U)
160 case 16:
161 resolution = kADC16_Resolution16Bit;
162 break;
163 #endif
164 default:
165 LOG_ERR("Invalid resolution");
166 return -EINVAL;
167 }
168
169 tmp32 = base->CFG1 & ~(ADC_CFG1_MODE_MASK);
170 tmp32 |= ADC_CFG1_MODE(resolution);
171 base->CFG1 = tmp32;
172
173 switch (sequence->oversampling) {
174 case 0:
175 mode = kADC16_HardwareAverageDisabled;
176 break;
177 case 2:
178 mode = kADC16_HardwareAverageCount4;
179 break;
180 case 3:
181 mode = kADC16_HardwareAverageCount8;
182 break;
183 case 4:
184 mode = kADC16_HardwareAverageCount16;
185 break;
186 case 5:
187 mode = kADC16_HardwareAverageCount32;
188 break;
189 default:
190 LOG_ERR("Invalid oversampling");
191 return -EINVAL;
192 }
193 ADC16_SetHardwareAverage(config->base, mode);
194
195 if (sequence->buffer_size < 2) {
196 LOG_ERR("sequence buffer size too small %d < 2", sequence->buffer_size);
197 return -EINVAL;
198 }
199
200 if (sequence->options) {
201 if (sequence->buffer_size <
202 2 * (sequence->options->extra_samplings + 1)) {
203 LOG_ERR("sequence buffer size too small < 2 * extra + 2");
204 return -EINVAL;
205 }
206 }
207
208 data->buffer = sequence->buffer;
209
210 adc_context_start_read(&data->ctx, sequence);
211
212 error = adc_context_wait_for_completion(&data->ctx);
213 #ifdef CONFIG_ADC_MCUX_ADC16_ENABLE_EDMA
214 dma_stop(data->dev_dma, data->adc_dma_config.dma_channel);
215 #endif
216 return error;
217 }
218
mcux_adc16_read(const struct device * dev,const struct adc_sequence * sequence)219 static int mcux_adc16_read(const struct device *dev,
220 const struct adc_sequence *sequence)
221 {
222 struct mcux_adc16_data *data = dev->data;
223 int error;
224
225 adc_context_lock(&data->ctx, false, NULL);
226 error = start_read(dev, sequence);
227 adc_context_release(&data->ctx, error);
228
229 return error;
230 }
231
232 #ifdef CONFIG_ADC_ASYNC
mcux_adc16_read_async(const struct device * dev,const struct adc_sequence * sequence,struct k_poll_signal * async)233 static int mcux_adc16_read_async(const struct device *dev,
234 const struct adc_sequence *sequence,
235 struct k_poll_signal *async)
236 {
237 struct mcux_adc16_data *data = dev->data;
238 int error;
239
240 adc_context_lock(&data->ctx, true, async);
241 error = start_read(dev, sequence);
242 adc_context_release(&data->ctx, error);
243
244 return error;
245 }
246 #endif
247
mcux_adc16_start_channel(const struct device * dev)248 static void mcux_adc16_start_channel(const struct device *dev)
249 {
250 const struct mcux_adc16_config *config = dev->config;
251 struct mcux_adc16_data *data = dev->data;
252
253 adc16_channel_config_t channel_config;
254 uint32_t channel_group = 0U;
255
256 data->channel_id = find_lsb_set(data->channels) - 1;
257
258 LOG_DBG("Starting channel %d", data->channel_id);
259
260 #if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE
261 channel_config.enableDifferentialConversion = false;
262 #endif
263 channel_config.enableInterruptOnConversionCompleted = true;
264 channel_config.channelNumber = data->channel_id;
265 ADC16_SetChannelConfig(config->base, channel_group, &channel_config);
266 #ifdef CONFIG_ADC_MCUX_ADC16_ENABLE_EDMA
267 LOG_DBG("Starting EDMA");
268 dma_start(data->dev_dma, data->adc_dma_config.dma_channel);
269 #endif
270 LOG_DBG("Starting channel done");
271 }
272
adc_context_start_sampling(struct adc_context * ctx)273 static void adc_context_start_sampling(struct adc_context *ctx)
274 {
275 struct mcux_adc16_data *data =
276 CONTAINER_OF(ctx, struct mcux_adc16_data, ctx);
277
278 data->channels = ctx->sequence.channels;
279 data->repeat_buffer = data->buffer;
280
281 #ifdef CONFIG_ADC_MCUX_ADC16_ENABLE_EDMA
282 LOG_DBG("config dma");
283 data->adc_dma_config.dma_block.block_size = 2;
284 data->adc_dma_config.dma_block.dest_address = (uint32_t)data->buffer;
285 data->adc_dma_config.dma_cfg.head_block =
286 &(data->adc_dma_config.dma_block);
287 dma_config(data->dev_dma, data->adc_dma_config.dma_channel,
288 &data->adc_dma_config.dma_cfg);
289 #endif
290
291 mcux_adc16_start_channel(data->dev);
292 }
293
adc_context_update_buffer_pointer(struct adc_context * ctx,bool repeat_sampling)294 static void adc_context_update_buffer_pointer(struct adc_context *ctx,
295 bool repeat_sampling)
296 {
297 struct mcux_adc16_data *data =
298 CONTAINER_OF(ctx, struct mcux_adc16_data, ctx);
299
300 if (repeat_sampling) {
301 data->buffer = data->repeat_buffer;
302 }
303 }
304
305 #ifndef CONFIG_ADC_MCUX_ADC16_ENABLE_EDMA
mcux_adc16_isr(const struct device * dev)306 static void mcux_adc16_isr(const struct device *dev)
307 {
308 const struct mcux_adc16_config *config = dev->config;
309 struct mcux_adc16_data *data = dev->data;
310 ADC_Type *base = config->base;
311 uint32_t channel_group = 0U;
312 uint16_t result;
313
314 result = ADC16_GetChannelConversionValue(base, channel_group);
315 LOG_DBG("Finished channel %d. Result is 0x%04x", data->channel_id,
316 result);
317
318 *data->buffer++ = result;
319 data->channels &= ~BIT(data->channel_id);
320
321 if (data->channels) {
322 mcux_adc16_start_channel(dev);
323 } else {
324 adc_context_on_sampling_done(&data->ctx, dev);
325 }
326 }
327 #endif
328
mcux_adc16_init(const struct device * dev)329 static int mcux_adc16_init(const struct device *dev)
330 {
331 const struct mcux_adc16_config *config = dev->config;
332 struct mcux_adc16_data *data = dev->data;
333 ADC_Type *base = config->base;
334 adc16_config_t adc_config;
335 int err;
336
337 LOG_DBG("init adc");
338 ADC16_GetDefaultConfig(&adc_config);
339
340 #ifdef CONFIG_ADC_MCUX_ADC16_ENABLE_EDMA
341 adc_config.clockSource = (adc16_clock_source_t)config->clk_source;
342 adc_config.longSampleMode =
343 (adc16_long_sample_mode_t)config->long_sample;
344 adc_config.enableHighSpeed = config->high_speed;
345 adc_config.enableContinuousConversion = config->continuous_convert;
346 #endif
347
348 #if CONFIG_ADC_MCUX_ADC16_VREF_DEFAULT
349 adc_config.referenceVoltageSource = kADC16_ReferenceVoltageSourceVref;
350 #else /* CONFIG_ADC_MCUX_ADC16_VREF_ALTERNATE */
351 adc_config.referenceVoltageSource = kADC16_ReferenceVoltageSourceValt;
352 #endif
353
354 #if CONFIG_ADC_MCUX_ADC16_CLK_DIV_RATIO_1
355 adc_config.clockDivider = kADC16_ClockDivider1;
356 #elif CONFIG_ADC_MCUX_ADC16_CLK_DIV_RATIO_2
357 adc_config.clockDivider = kADC16_ClockDivider2;
358 #elif CONFIG_ADC_MCUX_ADC16_CLK_DIV_RATIO_4
359 adc_config.clockDivider = kADC16_ClockDivider4;
360 #else /* CONFIG_ADC_MCUX_ADC16_CLK_DIV_RATIO_8 */
361 adc_config.clockDivider = kADC16_ClockDivider8;
362 #endif
363
364 ADC16_Init(base, &adc_config);
365 #if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && \
366 FSL_FEATURE_ADC16_HAS_CALIBRATION
367 ADC16_SetHardwareAverage(base, kADC16_HardwareAverageCount32);
368 ADC16_DoAutoCalibration(base);
369 #endif
370 if (config->channel_mux_b) {
371 ADC16_SetChannelMuxMode(base, kADC16_ChannelMuxB);
372 }
373
374 if (IS_ENABLED(CONFIG_ADC_MCUX_ADC16_HW_TRIGGER)) {
375 ADC16_EnableHardwareTrigger(base, true);
376 } else {
377 ADC16_EnableHardwareTrigger(base, false);
378 }
379
380 err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
381 if (err != 0) {
382 return err;
383 }
384
385 data->dev = dev;
386
387 /* dma related init */
388 #ifdef CONFIG_ADC_MCUX_ADC16_ENABLE_EDMA
389 /* Enable DMA. */
390 ADC16_EnableDMA(base, true);
391 data->adc_dma_config.dma_cfg.block_count = 1U;
392 data->adc_dma_config.dma_cfg.dma_slot = config->dma_slot;
393 data->adc_dma_config.dma_cfg.channel_direction = PERIPHERAL_TO_MEMORY;
394 data->adc_dma_config.dma_cfg.source_burst_length = 2U;
395 data->adc_dma_config.dma_cfg.dest_burst_length = 2U;
396 data->adc_dma_config.dma_cfg.channel_priority = 0U;
397 data->adc_dma_config.dma_cfg.dma_callback = adc_dma_callback;
398 data->adc_dma_config.dma_cfg.user_data = (void *)dev;
399
400 data->adc_dma_config.dma_cfg.source_data_size = 2U;
401 data->adc_dma_config.dma_cfg.dest_data_size = 2U;
402 data->adc_dma_config.dma_block.source_address = (uint32_t)&base->R[0];
403
404 if (data->dev_dma == NULL || !device_is_ready(data->dev_dma)) {
405 LOG_ERR("dma binding fail");
406 return -EINVAL;
407 }
408
409 if (config->periodic_trigger) {
410 enum dma_channel_filter adc_filter = DMA_CHANNEL_PERIODIC;
411
412 data->adc_dma_config.dma_channel =
413 dma_request_channel(data->dev_dma, (void *)&adc_filter);
414 } else {
415 enum dma_channel_filter adc_filter = DMA_CHANNEL_NORMAL;
416
417 data->adc_dma_config.dma_channel =
418 dma_request_channel(data->dev_dma, (void *)&adc_filter);
419 }
420 if (data->adc_dma_config.dma_channel == -EINVAL) {
421 LOG_ERR("can not allocate dma channel");
422 return -EINVAL;
423 }
424 LOG_DBG("dma allocated channel %d", data->adc_dma_config.dma_channel);
425 #else
426 config->irq_config_func(dev);
427 #endif
428 LOG_DBG("adc init done");
429
430 adc_context_unlock_unconditionally(&data->ctx);
431
432 return 0;
433 }
434
435 static DEVICE_API(adc, mcux_adc16_driver_api) = {
436 .channel_setup = mcux_adc16_channel_setup,
437 .read = mcux_adc16_read,
438 #ifdef CONFIG_ADC_ASYNC
439 .read_async = mcux_adc16_read_async,
440 #endif
441 };
442
443 #ifdef CONFIG_ADC_MCUX_ADC16_ENABLE_EDMA
444 #define ADC16_MCUX_EDMA_INIT(n) \
445 .hw_trigger_src = \
446 DT_INST_PROP_OR(n, hw_trigger_src, 0), \
447 .dma_slot = DT_INST_DMAS_CELL_BY_IDX(n, 0, source), \
448 .trg_offset = DT_INST_CLOCKS_CELL_BY_IDX(n, 0, offset), \
449 .trg_bits = DT_INST_CLOCKS_CELL_BY_IDX(n, 0, bits), \
450 .alt_offset = DT_INST_CLOCKS_CELL_BY_IDX(n, 1, offset), \
451 .alt_bits = DT_INST_CLOCKS_CELL_BY_IDX(n, 1, bits),
452 #define ADC16_MCUX_EDMA_DATA(n) \
453 .dev_dma = DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_NAME(n, adc##n))
454 #define ADC16_MCUX_IRQ_INIT(n)
455 #define ADC16_MCUX_IRQ_DECLARE(n)
456 #else
457 #define ADC16_MCUX_EDMA_INIT(n)
458 #define ADC16_MCUX_EDMA_DATA(n)
459 #define ADC16_MCUX_IRQ_INIT(n) .irq_config_func = mcux_adc16_config_func_##n,
460 #define ADC16_MCUX_IRQ_DECLARE(n) \
461 static void mcux_adc16_config_func_##n(const struct device *dev) \
462 { \
463 IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \
464 mcux_adc16_isr, \
465 DEVICE_DT_INST_GET(n), 0); \
466 \
467 irq_enable(DT_INST_IRQN(n)); \
468 }
469 #endif /* CONFIG_ADC_MCUX_ADC16_ENABLE_EDMA */
470
471
472 #define ACD16_MCUX_INIT(n) \
473 ADC16_MCUX_IRQ_DECLARE(n) \
474 PINCTRL_DT_INST_DEFINE(n); \
475 \
476 static const struct mcux_adc16_config mcux_adc16_config_##n = { \
477 .base = (ADC_Type *)DT_INST_REG_ADDR(n), \
478 ADC16_MCUX_IRQ_INIT(n) \
479 .channel_mux_b = DT_INST_PROP(n, channel_mux_b), \
480 .clk_source = DT_INST_PROP_OR(n, clk_source, 0), \
481 .long_sample = DT_INST_PROP_OR(n, long_sample, 0), \
482 .high_speed = DT_INST_PROP(n, high_speed), \
483 .periodic_trigger = DT_INST_PROP(n, periodic_trigger), \
484 .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
485 .continuous_convert = \
486 DT_INST_PROP(n, continuous_convert), \
487 ADC16_MCUX_EDMA_INIT(n) \
488 }; \
489 \
490 static struct mcux_adc16_data mcux_adc16_data_##n = { \
491 ADC_CONTEXT_INIT_TIMER(mcux_adc16_data_##n, ctx), \
492 ADC_CONTEXT_INIT_LOCK(mcux_adc16_data_##n, ctx), \
493 ADC_CONTEXT_INIT_SYNC(mcux_adc16_data_##n, ctx), \
494 ADC16_MCUX_EDMA_DATA(n) \
495 }; \
496 \
497 DEVICE_DT_INST_DEFINE(n, &mcux_adc16_init, \
498 NULL, \
499 &mcux_adc16_data_##n, \
500 &mcux_adc16_config_##n, \
501 POST_KERNEL, \
502 CONFIG_ADC_INIT_PRIORITY, \
503 &mcux_adc16_driver_api); \
504
505 DT_INST_FOREACH_STATUS_OKAY(ACD16_MCUX_INIT)
506
