1 /*
2 * Copyright (c) 2022 BrainCo Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT gd_gd32_adc
8
9 #include <errno.h>
10
11 #include <zephyr/drivers/clock_control.h>
12 #include <zephyr/drivers/clock_control/gd32.h>
13 #include <zephyr/drivers/pinctrl.h>
14 #include <zephyr/drivers/adc.h>
15 #include <zephyr/drivers/reset.h>
16 #include <zephyr/devicetree.h>
17 #include <zephyr/irq.h>
18
19 #include <gd32_adc.h>
20 #include <gd32_rcu.h>
21
22 #define ADC_CONTEXT_USES_KERNEL_TIMER
23 #include "adc_context.h"
24
25 #include <zephyr/logging/log.h>
26 LOG_MODULE_REGISTER(adc_gd32, CONFIG_ADC_LOG_LEVEL);
27
28 /**
29 * @brief gd32 adc irq have some special cases as below:
30 * 1. adc number no larger than 3.
31 * 2. adc0 and adc1 share the same irq number.
32 * 3. For gd32f4xx, adc2 share the same irq number with adc0 and adc1.
33 *
34 * To cover this cases, gd32_adc driver use node-label 'adc0', 'adc1' and
35 * 'adc2' to handle gd32 adc irq config directly.'
36 *
37 * @note Sorry for the restriction, But new added gd32 adc node-label must be 'adc0',
38 * 'adc1' and 'adc2'.
39 */
40 #define ADC0_NODE DT_NODELABEL(adc0)
41 #define ADC1_NODE DT_NODELABEL(adc1)
42 #define ADC2_NODE DT_NODELABEL(adc2)
43
44 #define ADC0_ENABLE DT_NODE_HAS_STATUS(ADC0_NODE, okay)
45 #define ADC1_ENABLE DT_NODE_HAS_STATUS(ADC1_NODE, okay)
46 #define ADC2_ENABLE DT_NODE_HAS_STATUS(ADC2_NODE, okay)
47
48 #ifndef ADC0
49 /**
50 * @brief The name of gd32 ADC HAL are different between single and multi ADC SoCs.
51 * This adjust the single ADC SoC HAL, so we can call gd32 ADC HAL in a common way.
52 */
53 #undef ADC_STAT
54 #undef ADC_CTL0
55 #undef ADC_CTL1
56 #undef ADC_SAMPT0
57 #undef ADC_SAMPT1
58 #undef ADC_RSQ2
59 #undef ADC_RDATA
60
61 #define ADC_STAT(adc0) REG32((adc0) + 0x00000000U)
62 #define ADC_CTL0(adc0) REG32((adc0) + 0x00000004U)
63 #define ADC_CTL1(adc0) REG32((adc0) + 0x00000008U)
64 #define ADC_SAMPT0(adc0) REG32((adc0) + 0x0000000CU)
65 #define ADC_SAMPT1(adc0) REG32((adc0) + 0x00000010U)
66 #define ADC_RSQ2(adc0) REG32((adc0) + 0x00000034U)
67 #define ADC_RDATA(adc0) REG32((adc0) + 0x0000004CU)
68 #endif
69
70 #define SPT_WIDTH 3U
71 #define SAMPT1_SIZE 10U
72
73 #if defined(CONFIG_SOC_SERIES_GD32F4XX)
74 #define SMP_TIME(x) ADC_SAMPLETIME_##x
75
76 static const uint16_t acq_time_tbl[8] = {3, 15, 28, 56, 84, 112, 144, 480};
77 static const uint32_t table_samp_time[] = {
78 SMP_TIME(3),
79 SMP_TIME(15),
80 SMP_TIME(28),
81 SMP_TIME(56),
82 SMP_TIME(84),
83 SMP_TIME(112),
84 SMP_TIME(144),
85 SMP_TIME(480)
86 };
87 #elif defined(CONFIG_SOC_SERIES_GD32L23X)
88 #define SMP_TIME(x) ADC_SAMPLETIME_##x##POINT5
89
90 static const uint16_t acq_time_tbl[8] = {3, 8, 14, 29, 42, 56, 72, 240};
91 static const uint32_t table_samp_time[] = {
92 SMP_TIME(2),
93 SMP_TIME(7),
94 SMP_TIME(13),
95 SMP_TIME(28),
96 SMP_TIME(41),
97 SMP_TIME(55),
98 SMP_TIME(71),
99 SMP_TIME(239),
100 };
101 #elif defined(CONFIG_SOC_SERIES_GD32A50X)
102 #define SMP_TIME(x) ADC_SAMPLETIME_##x##POINT5
103
104 static const uint16_t acq_time_tbl[8] = {3, 15, 28, 56, 84, 112, 144, 480};
105 static const uint32_t table_samp_time[] = {
106 SMP_TIME(2),
107 SMP_TIME(14),
108 SMP_TIME(27),
109 SMP_TIME(55),
110 SMP_TIME(83),
111 SMP_TIME(111),
112 SMP_TIME(143),
113 SMP_TIME(479)
114 };
115 #else
116 #define SMP_TIME(x) ADC_SAMPLETIME_##x##POINT5
117
118 static const uint16_t acq_time_tbl[8] = {2, 8, 14, 29, 42, 56, 72, 240};
119 static const uint32_t table_samp_time[] = {
120 SMP_TIME(1),
121 SMP_TIME(7),
122 SMP_TIME(13),
123 SMP_TIME(28),
124 SMP_TIME(41),
125 SMP_TIME(55),
126 SMP_TIME(71),
127 SMP_TIME(239)
128 };
129 #endif
130
131 struct adc_gd32_config {
132 uint32_t reg;
133 #ifdef CONFIG_SOC_SERIES_GD32F3X0
134 uint32_t rcu_clock_source;
135 #endif
136 uint16_t clkid;
137 struct reset_dt_spec reset;
138 uint8_t channels;
139 const struct pinctrl_dev_config *pcfg;
140 uint8_t irq_num;
141 void (*irq_config_func)(void);
142 };
143
144 struct adc_gd32_data {
145 struct adc_context ctx;
146 const struct device *dev;
147 uint16_t *buffer;
148 uint16_t *repeat_buffer;
149 };
150
adc_gd32_isr(const struct device * dev)151 static void adc_gd32_isr(const struct device *dev)
152 {
153 struct adc_gd32_data *data = dev->data;
154 const struct adc_gd32_config *cfg = dev->config;
155
156 if (ADC_STAT(cfg->reg) & ADC_STAT_EOC) {
157 *data->buffer++ = ADC_RDATA(cfg->reg);
158
159 /* Disable EOC interrupt. */
160 ADC_CTL0(cfg->reg) &= ~ADC_CTL0_EOCIE;
161 /* Clear EOC bit. */
162 ADC_STAT(cfg->reg) &= ~ADC_STAT_EOC;
163
164 adc_context_on_sampling_done(&data->ctx, dev);
165 }
166 }
167
adc_context_start_sampling(struct adc_context * ctx)168 static void adc_context_start_sampling(struct adc_context *ctx)
169 {
170 struct adc_gd32_data *data = CONTAINER_OF(ctx, struct adc_gd32_data, ctx);
171 const struct device *dev = data->dev;
172 const struct adc_gd32_config *cfg = dev->config;
173
174 data->repeat_buffer = data->buffer;
175
176 /* Enable EOC interrupt */
177 ADC_CTL0(cfg->reg) |= ADC_CTL0_EOCIE;
178
179 /* Set ADC software conversion trigger. */
180 ADC_CTL1(cfg->reg) |= ADC_CTL1_SWRCST;
181 }
182
adc_context_update_buffer_pointer(struct adc_context * ctx,bool repeat_sampling)183 static void adc_context_update_buffer_pointer(struct adc_context *ctx,
184 bool repeat_sampling)
185 {
186 struct adc_gd32_data *data = CONTAINER_OF(ctx, struct adc_gd32_data, ctx);
187
188 if (repeat_sampling) {
189 data->buffer = data->repeat_buffer;
190 }
191 }
192
adc_gd32_calibration(const struct adc_gd32_config * cfg)193 static inline void adc_gd32_calibration(const struct adc_gd32_config *cfg)
194 {
195 ADC_CTL1(cfg->reg) |= ADC_CTL1_RSTCLB;
196 /* Wait for calibration registers initialized. */
197 while (ADC_CTL1(cfg->reg) & ADC_CTL1_RSTCLB) {
198 }
199
200 ADC_CTL1(cfg->reg) |= ADC_CTL1_CLB;
201 /* Wait for calibration complete. */
202 while (ADC_CTL1(cfg->reg) & ADC_CTL1_CLB) {
203 }
204 }
205
adc_gd32_configure_sampt(const struct adc_gd32_config * cfg,uint8_t channel,uint16_t acq_time)206 static int adc_gd32_configure_sampt(const struct adc_gd32_config *cfg,
207 uint8_t channel, uint16_t acq_time)
208 {
209 uint8_t index = 0, offset;
210
211 if (acq_time != ADC_ACQ_TIME_DEFAULT) {
212 /* Acquisition time unit is adc clock cycle. */
213 if (ADC_ACQ_TIME_UNIT(acq_time) != ADC_ACQ_TIME_TICKS) {
214 return -EINVAL;
215 }
216
217 for ( ; index < ARRAY_SIZE(acq_time_tbl); index++) {
218 if (ADC_ACQ_TIME_VALUE(acq_time) <= acq_time_tbl[index]) {
219 break;
220 }
221 }
222
223 if (ADC_ACQ_TIME_VALUE(acq_time) != acq_time_tbl[index]) {
224 return -ENOTSUP;
225 }
226 }
227
228 if (channel < SAMPT1_SIZE) {
229 offset = SPT_WIDTH * channel;
230 ADC_SAMPT1(cfg->reg) &= ~(ADC_SAMPTX_SPTN << offset);
231 ADC_SAMPT1(cfg->reg) |= table_samp_time[index] << offset;
232 } else {
233 offset = SPT_WIDTH * (channel - SAMPT1_SIZE);
234 ADC_SAMPT0(cfg->reg) &= ~(ADC_SAMPTX_SPTN << offset);
235 ADC_SAMPT0(cfg->reg) |= table_samp_time[index] << offset;
236 }
237
238 return 0;
239 }
240
adc_gd32_channel_setup(const struct device * dev,const struct adc_channel_cfg * chan_cfg)241 static int adc_gd32_channel_setup(const struct device *dev,
242 const struct adc_channel_cfg *chan_cfg)
243 {
244 const struct adc_gd32_config *cfg = dev->config;
245
246 if (chan_cfg->gain != ADC_GAIN_1) {
247 LOG_ERR("Gain is not valid");
248 return -ENOTSUP;
249 }
250
251 if (chan_cfg->reference != ADC_REF_INTERNAL) {
252 LOG_ERR("Reference is not valid");
253 return -ENOTSUP;
254 }
255
256 if (chan_cfg->differential) {
257 LOG_ERR("Differential sampling not supported");
258 return -ENOTSUP;
259 }
260
261 if (chan_cfg->channel_id >= cfg->channels) {
262 LOG_ERR("Invalid channel (%u)", chan_cfg->channel_id);
263 return -EINVAL;
264 }
265
266 return adc_gd32_configure_sampt(cfg, chan_cfg->channel_id,
267 chan_cfg->acquisition_time);
268 }
269
adc_gd32_start_read(const struct device * dev,const struct adc_sequence * sequence)270 static int adc_gd32_start_read(const struct device *dev,
271 const struct adc_sequence *sequence)
272 {
273 struct adc_gd32_data *data = dev->data;
274 const struct adc_gd32_config *cfg = dev->config;
275 uint8_t resolution_id;
276 uint32_t index;
277
278 index = find_lsb_set(sequence->channels) - 1;
279 if (sequence->channels > BIT(index)) {
280 LOG_ERR("Only single channel supported");
281 return -ENOTSUP;
282 }
283
284 switch (sequence->resolution) {
285 case 12U:
286 resolution_id = 0U;
287 break;
288 case 10U:
289 resolution_id = 1U;
290 break;
291 case 8U:
292 resolution_id = 2U;
293 break;
294 case 6U:
295 resolution_id = 3U;
296 break;
297 default:
298 return -EINVAL;
299 }
300
301 #if defined(CONFIG_SOC_SERIES_GD32F4XX) || \
302 defined(CONFIG_SOC_SERIES_GD32F3X0) || \
303 defined(CONFIG_SOC_SERIES_GD32L23X)
304 ADC_CTL0(cfg->reg) &= ~ADC_CTL0_DRES;
305 ADC_CTL0(cfg->reg) |= CTL0_DRES(resolution_id);
306 #elif defined(CONFIG_SOC_SERIES_GD32F403) || \
307 defined(CONFIG_SOC_SERIES_GD32A50X)
308 ADC_OVSAMPCTL(cfg->reg) &= ~ADC_OVSAMPCTL_DRES;
309 ADC_OVSAMPCTL(cfg->reg) |= OVSAMPCTL_DRES(resolution_id);
310 #elif defined(CONFIG_SOC_SERIES_GD32VF103)
311 ADC_OVSCR(cfg->reg) &= ~ADC_OVSCR_DRES;
312 ADC_OVSCR(cfg->reg) |= OVSCR_DRES(resolution_id);
313 #endif
314
315 if (sequence->calibrate) {
316 adc_gd32_calibration(cfg);
317 }
318
319 /* Signle conversion mode with regular group. */
320 ADC_RSQ2(cfg->reg) &= ~ADC_RSQX_RSQN;
321 ADC_RSQ2(cfg->reg) = index;
322
323 data->buffer = sequence->buffer;
324
325 adc_context_start_read(&data->ctx, sequence);
326
327 return adc_context_wait_for_completion(&data->ctx);
328 }
329
adc_gd32_read(const struct device * dev,const struct adc_sequence * sequence)330 static int adc_gd32_read(const struct device *dev,
331 const struct adc_sequence *sequence)
332 {
333 struct adc_gd32_data *data = dev->data;
334 int error;
335
336 adc_context_lock(&data->ctx, false, NULL);
337 error = adc_gd32_start_read(dev, sequence);
338 adc_context_release(&data->ctx, error);
339
340 return error;
341 }
342
343 #ifdef CONFIG_ADC_ASYNC
adc_gd32_read_async(const struct device * dev,const struct adc_sequence * sequence,struct k_poll_signal * async)344 static int adc_gd32_read_async(const struct device *dev,
345 const struct adc_sequence *sequence,
346 struct k_poll_signal *async)
347 {
348 struct adc_gd32_data *data = dev->data;
349 int error;
350
351 adc_context_lock(&data->ctx, true, async);
352 error = adc_gd32_start_read(dev, sequence);
353 adc_context_release(&data->ctx, error);
354
355 return error;
356 }
357 #endif /* CONFIG_ADC_ASYNC */
358
359 static struct adc_driver_api adc_gd32_driver_api = {
360 .channel_setup = adc_gd32_channel_setup,
361 .read = adc_gd32_read,
362 #ifdef CONFIG_ADC_ASYNC
363 .read_async = adc_gd32_read_async,
364 #endif /* CONFIG_ADC_ASYNC */
365 };
366
adc_gd32_init(const struct device * dev)367 static int adc_gd32_init(const struct device *dev)
368 {
369 struct adc_gd32_data *data = dev->data;
370 const struct adc_gd32_config *cfg = dev->config;
371 int ret;
372
373 data->dev = dev;
374
375 ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
376 if (ret < 0) {
377 return ret;
378 }
379
380 #ifdef CONFIG_SOC_SERIES_GD32F3X0
381 /* Select adc clock source and its prescaler. */
382 rcu_adc_clock_config(cfg->rcu_clock_source);
383 #endif
384
385 (void)clock_control_on(GD32_CLOCK_CONTROLLER,
386 (clock_control_subsys_t)&cfg->clkid);
387
388 (void)reset_line_toggle_dt(&cfg->reset);
389
390 #if defined(CONFIG_SOC_SERIES_GD32F403) || \
391 defined(CONFIG_SOC_SERIES_GD32VF103) || \
392 defined(CONFIG_SOC_SERIES_GD32F3X0) || \
393 defined(CONFIG_SOC_SERIES_GD32L23X)
394 /* Set SWRCST as the regular channel external trigger. */
395 ADC_CTL1(cfg->reg) &= ~ADC_CTL1_ETSRC;
396 ADC_CTL1(cfg->reg) |= CTL1_ETSRC(7);
397
398 /* Enable external trigger for regular channel. */
399 ADC_CTL1(cfg->reg) |= ADC_CTL1_ETERC;
400 #endif
401
402 #ifdef CONFIG_SOC_SERIES_GD32A50X
403 ADC_CTL1(cfg->reg) |= ADC_CTL1_ETSRC;
404 ADC_CTL1(cfg->reg) |= ADC_CTL1_ETERC;
405 #endif
406
407 /* Enable ADC */
408 ADC_CTL1(cfg->reg) |= ADC_CTL1_ADCON;
409
410 adc_gd32_calibration(cfg);
411
412 cfg->irq_config_func();
413
414 adc_context_unlock_unconditionally(&data->ctx);
415
416 return 0;
417 }
418
419 #define HANDLE_SHARED_IRQ(n, active_irq) \
420 static const struct device *const dev_##n = DEVICE_DT_INST_GET(n); \
421 const struct adc_gd32_config *cfg_##n = dev_##n->config; \
422 \
423 if ((cfg_##n->irq_num == active_irq) && \
424 (ADC_CTL0(cfg_##n->reg) & ADC_CTL0_EOCIE)) { \
425 adc_gd32_isr(dev_##n); \
426 }
427
adc_gd32_global_irq_handler(const struct device * dev)428 static void adc_gd32_global_irq_handler(const struct device *dev)
429 {
430 const struct adc_gd32_config *cfg = dev->config;
431
432 LOG_DBG("global irq handler: %u", cfg->irq_num);
433
434 DT_INST_FOREACH_STATUS_OKAY_VARGS(HANDLE_SHARED_IRQ, (cfg->irq_num));
435 }
436
adc_gd32_global_irq_cfg(void)437 static void adc_gd32_global_irq_cfg(void)
438 {
439 static bool global_irq_init = true;
440
441 if (!global_irq_init) {
442 return;
443 }
444
445 global_irq_init = false;
446
447 #if ADC0_ENABLE
448 /* Shared irq config default to adc0. */
449 IRQ_CONNECT(DT_IRQN(ADC0_NODE),
450 DT_IRQ(ADC0_NODE, priority),
451 adc_gd32_global_irq_handler,
452 DEVICE_DT_GET(ADC0_NODE),
453 0);
454 irq_enable(DT_IRQN(ADC0_NODE));
455 #elif ADC1_ENABLE
456 IRQ_CONNECT(DT_IRQN(ADC1_NODE),
457 DT_IRQ(ADC1_NODE, priority),
458 adc_gd32_global_irq_handler,
459 DEVICE_DT_GET(ADC1_NODE),
460 0);
461 irq_enable(DT_IRQN(ADC1_NODE));
462 #endif
463
464 #if (ADC0_ENABLE || ADC1_ENABLE) && \
465 defined(CONFIG_SOC_SERIES_GD32F4XX)
466 /* gd32f4xx adc2 share the same irq number with adc0 and adc1. */
467 #elif ADC2_ENABLE
468 IRQ_CONNECT(DT_IRQN(ADC2_NODE),
469 DT_IRQ(ADC2_NODE, priority),
470 adc_gd32_global_irq_handler,
471 DEVICE_DT_GET(ADC2_NODE),
472 0);
473 irq_enable(DT_IRQN(ADC2_NODE));
474 #endif
475 }
476
477 #ifdef CONFIG_SOC_SERIES_GD32F3X0
478 #define ADC_CLOCK_SOURCE(n) \
479 .rcu_clock_source = DT_INST_PROP(n, rcu_clock_source)
480 #else
481 #define ADC_CLOCK_SOURCE(n)
482 #endif
483
484 #define ADC_GD32_INIT(n) \
485 PINCTRL_DT_INST_DEFINE(n); \
486 static struct adc_gd32_data adc_gd32_data_##n = { \
487 ADC_CONTEXT_INIT_TIMER(adc_gd32_data_##n, ctx), \
488 ADC_CONTEXT_INIT_LOCK(adc_gd32_data_##n, ctx), \
489 ADC_CONTEXT_INIT_SYNC(adc_gd32_data_##n, ctx), \
490 }; \
491 const static struct adc_gd32_config adc_gd32_config_##n = { \
492 .reg = DT_INST_REG_ADDR(n), \
493 .clkid = DT_INST_CLOCKS_CELL(n, id), \
494 .reset = RESET_DT_SPEC_INST_GET(n), \
495 .channels = DT_INST_PROP(n, channels), \
496 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
497 .irq_num = DT_INST_IRQN(n), \
498 .irq_config_func = adc_gd32_global_irq_cfg, \
499 ADC_CLOCK_SOURCE(n) \
500 }; \
501 DEVICE_DT_INST_DEFINE(n, \
502 &adc_gd32_init, NULL, \
503 &adc_gd32_data_##n, &adc_gd32_config_##n, \
504 POST_KERNEL, CONFIG_ADC_INIT_PRIORITY, \
505 &adc_gd32_driver_api); \
506
507 DT_INST_FOREACH_STATUS_OKAY(ADC_GD32_INIT)
508
