1 /*
2 * Copyright (c) 2022 Florin Stancu <niflostancu@gmail.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT ti_cc13xx_cc26xx_adc
8
9 #include <errno.h>
10
11 #define LOG_LEVEL CONFIG_ADC_LOG_LEVEL
12 #include <zephyr/logging/log.h>
13 LOG_MODULE_REGISTER(adc_cc13xx_cc26xx);
14
15 #include <zephyr/device.h>
16 #include <zephyr/kernel.h>
17 #include <zephyr/init.h>
18 #include <zephyr/drivers/adc.h>
19 #include <soc.h>
20
21 /* Driverlib includes */
22 #include <inc/hw_types.h>
23 #include <driverlib/interrupt.h>
24 #include <driverlib/ioc.h>
25 #include <driverlib/rom.h>
26 #include <driverlib/prcm.h>
27 #include <driverlib/aux_adc.h>
28 #include <ti/devices/cc13x2_cc26x2/inc/hw_aux_evctl.h>
29
30 #define ADC_CONTEXT_USES_KERNEL_TIMER
31 #include "adc_context.h"
32
33
34 /**
35 * Channels are based on ADC_COMPB_IN_* hal_ti definitions, max. index is 16 (included).
36 */
37 #define MAX_CHAN_ID 0x10
38
39 /** Internal sample time unit conversion entry. */
40 struct adc_cc13xx_cc26xx_sample_time_entry {
41 uint16_t time_us;
42 uint8_t reg_value;
43 };
44
45 /** Maps standard unit sample times (us) to internal (raw hal_ti register) values */
46 static const struct adc_cc13xx_cc26xx_sample_time_entry adc_cc13xx_sample_times[] = {
47 { 2, AUXADC_SAMPLE_TIME_2P7_US },
48 { 5, AUXADC_SAMPLE_TIME_5P3_US },
49 { 10, AUXADC_SAMPLE_TIME_10P6_US },
50 { 21, AUXADC_SAMPLE_TIME_21P3_US },
51 { 42, AUXADC_SAMPLE_TIME_42P6_US },
52 { 85, AUXADC_SAMPLE_TIME_85P3_US },
53 { 170, AUXADC_SAMPLE_TIME_170_US },
54 { 341, AUXADC_SAMPLE_TIME_341_US },
55 { 682, AUXADC_SAMPLE_TIME_682_US },
56 { 1370, AUXADC_SAMPLE_TIME_1P37_MS },
57 { 2730, AUXADC_SAMPLE_TIME_2P73_MS },
58 { 5460, AUXADC_SAMPLE_TIME_5P46_MS },
59 { 10900, AUXADC_SAMPLE_TIME_10P9_MS },
60 };
61
62 struct adc_cc13xx_cc26xx_data {
63 struct adc_context ctx;
64 const struct device *dev;
65 uint32_t ref_source;
66 uint8_t sample_time;
67 uint16_t *buffer;
68 uint16_t *repeat_buffer;
69 };
70
71 struct adc_cc13xx_cc26xx_cfg {
72 unsigned long base;
73 void (*irq_cfg_func)(void);
74 };
75
76
77 static void adc_cc13xx_cc26xx_isr(const struct device *dev);
78
79
adc_context_start_sampling(struct adc_context * ctx)80 static void adc_context_start_sampling(struct adc_context *ctx)
81 {
82 struct adc_cc13xx_cc26xx_data *data =
83 CONTAINER_OF(ctx, struct adc_cc13xx_cc26xx_data, ctx);
84
85 data->repeat_buffer = data->buffer;
86
87 AUXADCEnableSync(data->ref_source, data->sample_time, AUXADC_TRIGGER_MANUAL);
88 AUXADCGenManualTrigger();
89 }
90
adc_context_update_buffer_pointer(struct adc_context * ctx,bool repeat)91 static void adc_context_update_buffer_pointer(struct adc_context *ctx,
92 bool repeat)
93 {
94 struct adc_cc13xx_cc26xx_data *data =
95 CONTAINER_OF(ctx, struct adc_cc13xx_cc26xx_data, ctx);
96
97 if (repeat) {
98 data->buffer = data->repeat_buffer;
99 } else {
100 data->buffer++;
101 }
102 }
103
adc_cc13xx_cc26xx_init(const struct device * dev)104 static int adc_cc13xx_cc26xx_init(const struct device *dev)
105 {
106 struct adc_cc13xx_cc26xx_data *data = dev->data;
107 const struct adc_cc13xx_cc26xx_cfg *config = dev->config;
108
109 data->dev = dev;
110
111 /* clear any previous events */
112 AUXADCDisable();
113 HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_EVTOMCUFLAGSCLR) =
114 (AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_IRQ | AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_DONE);
115
116 config->irq_cfg_func();
117
118 adc_context_unlock_unconditionally(&data->ctx);
119 return 0;
120 }
121
adc_cc13xx_cc26xx_channel_setup(const struct device * dev,const struct adc_channel_cfg * channel_cfg)122 static int adc_cc13xx_cc26xx_channel_setup(const struct device *dev,
123 const struct adc_channel_cfg *channel_cfg)
124 {
125 struct adc_cc13xx_cc26xx_data *data = dev->data;
126 const uint8_t ch = channel_cfg->channel_id;
127 uint16_t sample_time_us = 0;
128 uint8_t i;
129
130 if (ch > MAX_CHAN_ID) {
131 LOG_ERR("Channel 0x%X is not supported, max 0x%X", ch, MAX_CHAN_ID);
132 return -EINVAL;
133 }
134
135 switch (ADC_ACQ_TIME_UNIT(channel_cfg->acquisition_time)) {
136 case ADC_ACQ_TIME_TICKS:
137 data->sample_time = (uint16_t)ADC_ACQ_TIME_VALUE(channel_cfg->acquisition_time);
138 break;
139 case ADC_ACQ_TIME_MICROSECONDS:
140 sample_time_us = (uint16_t)ADC_ACQ_TIME_VALUE(channel_cfg->acquisition_time);
141 break;
142 case ADC_ACQ_TIME_NANOSECONDS:
143 sample_time_us = (uint16_t)(
144 ADC_ACQ_TIME_VALUE(channel_cfg->acquisition_time) * 1000);
145 break;
146 default:
147 data->sample_time = AUXADC_SAMPLE_TIME_170_US;
148 break;
149 }
150 if (sample_time_us) {
151 /* choose the nearest sample time configuration */
152 data->sample_time = adc_cc13xx_sample_times[0].reg_value;
153 for (i = 0; i < ARRAY_SIZE(adc_cc13xx_sample_times); i++) {
154 if (adc_cc13xx_sample_times[i].time_us >= sample_time_us) {
155 break;
156 }
157 data->sample_time = adc_cc13xx_sample_times[i].reg_value;
158 }
159 if (i >= ARRAY_SIZE(adc_cc13xx_sample_times)) {
160 LOG_ERR("Acquisition time is not valid");
161 return -EINVAL;
162 }
163 }
164
165 if (channel_cfg->differential) {
166 LOG_ERR("Differential channels are not supported");
167 return -EINVAL;
168 }
169
170 if (channel_cfg->gain != ADC_GAIN_1) {
171 LOG_ERR("Gain is not valid");
172 return -EINVAL;
173 }
174
175 if (channel_cfg->reference == ADC_REF_INTERNAL) {
176 data->ref_source = AUXADC_REF_FIXED;
177 } else if (channel_cfg->reference == ADC_REF_VDD_1) {
178 data->ref_source = AUXADC_REF_VDDS_REL;
179 } else {
180 LOG_ERR("Reference is not valid");
181 return -EINVAL;
182 }
183
184 LOG_DBG("Setup %d acq time %d", ch, data->sample_time);
185
186 AUXADCDisable();
187 AUXADCSelectInput(ch);
188 return 0;
189 }
190
cc13xx_cc26xx_read(const struct device * dev,const struct adc_sequence * sequence,bool asynchronous,struct k_poll_signal * sig)191 static int cc13xx_cc26xx_read(const struct device *dev,
192 const struct adc_sequence *sequence,
193 bool asynchronous,
194 struct k_poll_signal *sig)
195 {
196 struct adc_cc13xx_cc26xx_data *data = dev->data;
197 int rv;
198 size_t exp_size;
199
200 if (sequence->resolution != 12) {
201 LOG_ERR("Only 12 Resolution is supported, but %d got",
202 sequence->resolution);
203 return -EINVAL;
204 }
205
206 exp_size = sizeof(uint16_t);
207 if (sequence->options) {
208 exp_size *= (1 + sequence->options->extra_samplings);
209 }
210
211 if (sequence->buffer_size < exp_size) {
212 LOG_ERR("Required buffer size is %u, but %u got",
213 exp_size, sequence->buffer_size);
214 return -ENOMEM;
215 }
216
217 data->buffer = sequence->buffer;
218
219 adc_context_lock(&data->ctx, asynchronous, sig);
220 adc_context_start_read(&data->ctx, sequence);
221 rv = adc_context_wait_for_completion(&data->ctx);
222 adc_context_release(&data->ctx, rv);
223 return rv;
224 }
225
adc_cc13xx_cc26xx_read(const struct device * dev,const struct adc_sequence * sequence)226 static int adc_cc13xx_cc26xx_read(const struct device *dev,
227 const struct adc_sequence *sequence)
228 {
229 return cc13xx_cc26xx_read(dev, sequence, false, NULL);
230 }
231
232 #ifdef CONFIG_ADC_ASYNC
adc_cc13xx_cc26xx_read_async(const struct device * dev,const struct adc_sequence * sequence,struct k_poll_signal * async)233 static int adc_cc13xx_cc26xx_read_async(const struct device *dev,
234 const struct adc_sequence *sequence,
235 struct k_poll_signal *async)
236 {
237 return cc13xx_cc26xx_read(dev, sequence, true, async);
238 }
239 #endif
240
241 /**
242 * AUX_ADC_IRQ handler, called for either of these events:
243 * - conversion complete or DMA done (if used);
244 * - FIFO underflow or overflow;
245 */
adc_cc13xx_cc26xx_isr(const struct device * dev)246 static void adc_cc13xx_cc26xx_isr(const struct device *dev)
247 {
248 struct adc_cc13xx_cc26xx_data *data = dev->data;
249 /* get the statuses of ADC_DONE and ADC_IRQ events in order to clear them both */
250 uint32_t ev_status = (
251 HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_EVTOMCUFLAGS) &
252 (AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_IRQ | AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_DONE)
253 );
254 uint32_t fifo_status;
255 uint32_t adc_value;
256
257 /* clear the AUXADC-related event flags */
258 HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_EVTOMCUFLAGSCLR) = ev_status;
259 /* check the ADC FIFO's status */
260 fifo_status = AUXADCGetFifoStatus();
261 LOG_DBG("ISR flags 0x%08X fifo 0x%08X", ev_status, fifo_status);
262 if ((fifo_status & (AUX_ANAIF_ADCFIFOSTAT_OVERFLOW | AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW))) {
263 AUXADCFlushFifo();
264 }
265 if ((fifo_status & AUX_ANAIF_ADCFIFOSTAT_EMPTY_M)) {
266 /* no ADC values available */
267 return;
268 }
269 adc_value = AUXADCPopFifo();
270 LOG_DBG("ADC buf %04X val %d", (unsigned int)data->buffer, adc_value);
271 *data->buffer = adc_value;
272 AUXADCDisable();
273
274 adc_context_on_sampling_done(&data->ctx, dev);
275 }
276
277 static const struct adc_driver_api cc13xx_cc26xx_driver_api = {
278 .channel_setup = adc_cc13xx_cc26xx_channel_setup,
279 .read = adc_cc13xx_cc26xx_read,
280 #ifdef CONFIG_ADC_ASYNC
281 .read_async = adc_cc13xx_cc26xx_read_async,
282 #endif
283 .ref_internal = 4300, /* fixed reference: 4.3V */
284 };
285
286 #define CC13XX_CC26XX_ADC_INIT(index) \
287 static void adc_cc13xx_cc26xx_cfg_func_##index(void); \
288 static const struct adc_cc13xx_cc26xx_cfg adc_cc13xx_cc26xx_cfg_##index = { \
289 .base = DT_INST_REG_ADDR(index), \
290 .irq_cfg_func = adc_cc13xx_cc26xx_cfg_func_##index, \
291 }; \
292 static struct adc_cc13xx_cc26xx_data adc_cc13xx_cc26xx_data_##index = { \
293 ADC_CONTEXT_INIT_TIMER(adc_cc13xx_cc26xx_data_##index, ctx), \
294 ADC_CONTEXT_INIT_LOCK(adc_cc13xx_cc26xx_data_##index, ctx), \
295 ADC_CONTEXT_INIT_SYNC(adc_cc13xx_cc26xx_data_##index, ctx), \
296 }; \
297 DEVICE_DT_INST_DEFINE(index, \
298 &adc_cc13xx_cc26xx_init, NULL, \
299 &adc_cc13xx_cc26xx_data_##index, \
300 &adc_cc13xx_cc26xx_cfg_##index, POST_KERNEL, \
301 CONFIG_ADC_INIT_PRIORITY, \
302 &cc13xx_cc26xx_driver_api); \
303 \
304 static void adc_cc13xx_cc26xx_cfg_func_##index(void) \
305 { \
306 IRQ_CONNECT(DT_INST_IRQN(index), DT_INST_IRQ(index, priority), \
307 adc_cc13xx_cc26xx_isr, DEVICE_DT_INST_GET(index), 0); \
308 irq_enable(DT_INST_IRQN(index)); \
309 }
310
311 DT_INST_FOREACH_STATUS_OKAY(CC13XX_CC26XX_ADC_INIT)
312
