1 /*
2 * Copyright (c) 2023 SILA Embedded Solutions GmbH
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6 #include <zephyr/device.h>
7 #include <zephyr/devicetree.h>
8 #include <zephyr/drivers/adc.h>
9 #include <zephyr/drivers/adc/ads114s0x.h>
10 #include <zephyr/drivers/spi.h>
11 #include <zephyr/drivers/gpio.h>
12 #include <zephyr/dt-bindings/adc/ads114s0x_adc.h>
13 #include <zephyr/logging/log.h>
14 #include <zephyr/kernel.h>
15 #include <zephyr/sys/__assert.h>
16 #include <zephyr/sys/byteorder.h>
17 #include <zephyr/sys/util.h>
18
19 #define ADC_CONTEXT_USES_KERNEL_TIMER 1
20 #define ADC_CONTEXT_WAIT_FOR_COMPLETION_TIMEOUT \
21 K_MSEC(CONFIG_ADC_ADS114S0X_WAIT_FOR_COMPLETION_TIMEOUT_MS)
22 #include "adc_context.h"
23
24 LOG_MODULE_REGISTER(ads114s0x, CONFIG_ADC_LOG_LEVEL);
25
26 #define ADS114S0X_CLK_FREQ_IN_KHZ 4096
27 #define ADS114S0X_RESET_LOW_TIME_IN_CLOCK_CYCLES 4
28 #define ADS114S0X_START_SYNC_PULSE_DURATION_IN_CLOCK_CYCLES 4
29 #define ADS114S0X_SETUP_TIME_IN_CLOCK_CYCLES 32
30 #define ADS114S0X_INPUT_SELECTION_AINCOM 12
31 #define ADS114S0X_RESOLUTION 16
32 #define ADS114S0X_REF_INTERNAL 2500
33 #define ADS114S0X_GPIO_MAX 3
34 #define ADS114S0X_POWER_ON_RESET_TIME_IN_US 2200
35
36 /* Not mentioned in the datasheet, but instead determined experimentally. */
37 #define ADS114S0X_RESET_DELAY_TIME_SAFETY_MARGIN_IN_US 1000
38 #define ADS114S0X_RESET_DELAY_TIME_IN_US \
39 (4096 * 1000 / ADS114S0X_CLK_FREQ_IN_KHZ + ADS114S0X_RESET_DELAY_TIME_SAFETY_MARGIN_IN_US)
40
41 #define ADS114S0X_RESET_LOW_TIME_IN_US \
42 (ADS114S0X_RESET_LOW_TIME_IN_CLOCK_CYCLES * 1000 / ADS114S0X_CLK_FREQ_IN_KHZ)
43 #define ADS114S0X_START_SYNC_PULSE_DURATION_IN_US \
44 (ADS114S0X_START_SYNC_PULSE_DURATION_IN_CLOCK_CYCLES * 1000 / ADS114S0X_CLK_FREQ_IN_KHZ)
45 #define ADS114S0X_SETUP_TIME_IN_US \
46 (ADS114S0X_SETUP_TIME_IN_CLOCK_CYCLES * 1000 / ADS114S0X_CLK_FREQ_IN_KHZ)
47
48 enum ads114s0x_command {
49 ADS114S0X_COMMAND_NOP = 0x00,
50 ADS114S0X_COMMAND_WAKEUP = 0x02,
51 ADS114S0X_COMMAND_POWERDOWN = 0x04,
52 ADS114S0X_COMMAND_RESET = 0x06,
53 ADS114S0X_COMMAND_START = 0x08,
54 ADS114S0X_COMMAND_STOP = 0x0A,
55 ADS114S0X_COMMAND_SYOCAL = 0x16,
56 ADS114S0X_COMMAND_SYGCAL = 0x17,
57 ADS114S0X_COMMAND_SFOCAL = 0x19,
58 ADS114S0X_COMMAND_RDATA = 0x12,
59 ADS114S0X_COMMAND_RREG = 0x20,
60 ADS114S0X_COMMAND_WREG = 0x40,
61 };
62
63 enum ads114s0x_register {
64 ADS114S0X_REGISTER_ID = 0x00,
65 ADS114S0X_REGISTER_STATUS = 0x01,
66 ADS114S0X_REGISTER_INPMUX = 0x02,
67 ADS114S0X_REGISTER_PGA = 0x03,
68 ADS114S0X_REGISTER_DATARATE = 0x04,
69 ADS114S0X_REGISTER_REF = 0x05,
70 ADS114S0X_REGISTER_IDACMAG = 0x06,
71 ADS114S0X_REGISTER_IDACMUX = 0x07,
72 ADS114S0X_REGISTER_VBIAS = 0x08,
73 ADS114S0X_REGISTER_SYS = 0x09,
74 ADS114S0X_REGISTER_OFCAL0 = 0x0B,
75 ADS114S0X_REGISTER_OFCAL1 = 0x0C,
76 ADS114S0X_REGISTER_FSCAL0 = 0x0E,
77 ADS114S0X_REGISTER_FSCAL1 = 0x0F,
78 ADS114S0X_REGISTER_GPIODAT = 0x10,
79 ADS114S0X_REGISTER_GPIOCON = 0x11,
80 };
81
82 #define ADS114S0X_REGISTER_GET_VALUE(value, pos, length) \
83 FIELD_GET(GENMASK(pos + length - 1, pos), value)
84 #define ADS114S0X_REGISTER_SET_VALUE(target, value, pos, length) \
85 target &= ~GENMASK(pos + length - 1, pos); \
86 target |= FIELD_PREP(GENMASK(pos + length - 1, pos), value)
87
88 #define ADS114S0X_REGISTER_ID_DEV_ID_LENGTH 3
89 #define ADS114S0X_REGISTER_ID_DEV_ID_POS 0
90 #define ADS114S0X_REGISTER_ID_DEV_ID_GET(value) \
91 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_ID_DEV_ID_POS, \
92 ADS114S0X_REGISTER_ID_DEV_ID_LENGTH)
93 #define ADS114S0X_REGISTER_ID_DEV_ID_SET(target, value) \
94 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_ID_DEV_ID_POS, \
95 ADS114S0X_REGISTER_ID_DEV_ID_LENGTH)
96 #define ADS114S0X_REGISTER_STATUS_FL_POR_LENGTH 1
97 #define ADS114S0X_REGISTER_STATUS_FL_POR_POS 7
98 #define ADS114S0X_REGISTER_STATUS_FL_POR_GET(value) \
99 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_STATUS_FL_POR_POS, \
100 ADS114S0X_REGISTER_STATUS_FL_POR_LENGTH)
101 #define ADS114S0X_REGISTER_STATUS_FL_POR_SET(target, value) \
102 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_STATUS_FL_POR_POS, \
103 ADS114S0X_REGISTER_STATUS_FL_POR_LENGTH)
104 #define ADS114S0X_REGISTER_STATUS_NOT_RDY_LENGTH 1
105 #define ADS114S0X_REGISTER_STATUS_NOT_RDY_POS 6
106 #define ADS114S0X_REGISTER_STATUS_NOT_RDY_GET(value) \
107 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_STATUS_NOT_RDY_POS, \
108 ADS114S0X_REGISTER_STATUS_NOT_RDY_LENGTH)
109 #define ADS114S0X_REGISTER_STATUS_NOT_RDY_SET(target, value) \
110 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_STATUS_NOT_RDY_POS, \
111 ADS114S0X_REGISTER_STATUS_NOT_RDY_LENGTH)
112 #define ADS114S0X_REGISTER_STATUS_FL_P_RAILP_LENGTH 1
113 #define ADS114S0X_REGISTER_STATUS_FL_P_RAILP_POS 5
114 #define ADS114S0X_REGISTER_STATUS_FL_P_RAILP_GET(value) \
115 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_STATUS_FL_P_RAILP_POS, \
116 ADS114S0X_REGISTER_STATUS_FL_P_RAILP_LENGTH)
117 #define ADS114S0X_REGISTER_STATUS_FL_P_RAILP_SET(target, value) \
118 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_STATUS_FL_P_RAILP_POS, \
119 ADS114S0X_REGISTER_STATUS_FL_P_RAILP_LENGTH)
120 #define ADS114S0X_REGISTER_STATUS_FL_P_RAILN_LENGTH 1
121 #define ADS114S0X_REGISTER_STATUS_FL_P_RAILN_POS 4
122 #define ADS114S0X_REGISTER_STATUS_FL_P_RAILN_GET(value) \
123 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_STATUS_FL_P_RAILN_POS, \
124 ADS114S0X_REGISTER_STATUS_FL_P_RAILN_LENGTH)
125 #define ADS114S0X_REGISTER_STATUS_FL_P_RAILN_SET(target, value) \
126 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_STATUS_FL_P_RAILN_POS, \
127 ADS114S0X_REGISTER_STATUS_FL_P_RAILN_LENGTH)
128 #define ADS114S0X_REGISTER_STATUS_FL_N_RAILP_LENGTH 1
129 #define ADS114S0X_REGISTER_STATUS_FL_N_RAILP_POS 3
130 #define ADS114S0X_REGISTER_STATUS_FL_N_RAILP_GET(value) \
131 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_STATUS_FL_N_RAILP_POS, \
132 ADS114S0X_REGISTER_STATUS_FL_N_RAILP_LENGTH)
133 #define ADS114S0X_REGISTER_STATUS_FL_N_RAILP_SET(target, value) \
134 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_STATUS_FL_N_RAILP_POS, \
135 ADS114S0X_REGISTER_STATUS_FL_N_RAILP_LENGTH)
136 #define ADS114S0X_REGISTER_STATUS_FL_N_RAILN_LENGTH 1
137 #define ADS114S0X_REGISTER_STATUS_FL_N_RAILN_POS 2
138 #define ADS114S0X_REGISTER_STATUS_FL_N_RAILN_GET(value) \
139 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_STATUS_FL_N_RAILN_POS, \
140 ADS114S0X_REGISTER_STATUS_FL_N_RAILN_LENGTH)
141 #define ADS114S0X_REGISTER_STATUS_FL_N_RAILN_SET(target, value) \
142 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_STATUS_FL_N_RAILN_POS, \
143 ADS114S0X_REGISTER_STATUS_FL_N_RAILN_LENGTH)
144 #define ADS114S0X_REGISTER_STATUS_FL_REF_L1_LENGTH 1
145 #define ADS114S0X_REGISTER_STATUS_FL_REF_L1_POS 1
146 #define ADS114S0X_REGISTER_STATUS_FL_REF_L1_GET(value) \
147 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_STATUS_FL_REF_L1_POS, \
148 ADS114S0X_REGISTER_STATUS_FL_REF_L1_LENGTH)
149 #define ADS114S0X_REGISTER_STATUS_FL_REF_L1_SET(target, value) \
150 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_STATUS_FL_REF_L1_POS, \
151 ADS114S0X_REGISTER_STATUS_FL_REF_L1_LENGTH)
152 #define ADS114S0X_REGISTER_STATUS_FL_REF_L0_LENGTH 1
153 #define ADS114S0X_REGISTER_STATUS_FL_REF_L0_POS 0
154 #define ADS114S0X_REGISTER_STATUS_FL_REF_L0_GET(value) \
155 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_STATUS_FL_REF_L0_POS, \
156 ADS114S0X_REGISTER_STATUS_FL_REF_L0_LENGTH)
157 #define ADS114S0X_REGISTER_STATUS_FL_REF_L0_SET(target, value) \
158 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_STATUS_FL_REF_L0_POS, \
159 ADS114S0X_REGISTER_STATUS_FL_REF_L0_LENGTH)
160 #define ADS114S0X_REGISTER_INPMUX_MUXP_LENGTH 4
161 #define ADS114S0X_REGISTER_INPMUX_MUXP_POS 4
162 #define ADS114S0X_REGISTER_INPMUX_MUXP_GET(value) \
163 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_INPMUX_MUXP_POS, \
164 ADS114S0X_REGISTER_INPMUX_MUXP_LENGTH)
165 #define ADS114S0X_REGISTER_INPMUX_MUXP_SET(target, value) \
166 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_INPMUX_MUXP_POS, \
167 ADS114S0X_REGISTER_INPMUX_MUXP_LENGTH)
168 #define ADS114S0X_REGISTER_INPMUX_MUXN_LENGTH 4
169 #define ADS114S0X_REGISTER_INPMUX_MUXN_POS 0
170 #define ADS114S0X_REGISTER_INPMUX_MUXN_GET(value) \
171 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_INPMUX_MUXN_POS, \
172 ADS114S0X_REGISTER_INPMUX_MUXN_LENGTH)
173 #define ADS114S0X_REGISTER_INPMUX_MUXN_SET(target, value) \
174 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_INPMUX_MUXN_POS, \
175 ADS114S0X_REGISTER_INPMUX_MUXN_LENGTH)
176 #define ADS114S0X_REGISTER_PGA_DELAY_LENGTH 3
177 #define ADS114S0X_REGISTER_PGA_DELAY_POS 5
178 #define ADS114S0X_REGISTER_PGA_DELAY_GET(value) \
179 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_PGA_DELAY_POS, \
180 ADS114S0X_REGISTER_PGA_DELAY_LENGTH)
181 #define ADS114S0X_REGISTER_PGA_DELAY_SET(target, value) \
182 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_PGA_DELAY_POS, \
183 ADS114S0X_REGISTER_PGA_DELAY_LENGTH)
184 #define ADS114S0X_REGISTER_PGA_PGA_EN_LENGTH 2
185 #define ADS114S0X_REGISTER_PGA_PGA_EN_POS 3
186 #define ADS114S0X_REGISTER_PGA_PGA_EN_GET(value) \
187 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_PGA_PGA_EN_POS, \
188 ADS114S0X_REGISTER_PGA_PGA_EN_LENGTH)
189 #define ADS114S0X_REGISTER_PGA_PGA_EN_SET(target, value) \
190 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_PGA_PGA_EN_POS, \
191 ADS114S0X_REGISTER_PGA_PGA_EN_LENGTH)
192 #define ADS114S0X_REGISTER_PGA_GAIN_LENGTH 3
193 #define ADS114S0X_REGISTER_PGA_GAIN_POS 0
194 #define ADS114S0X_REGISTER_PGA_GAIN_GET(value) \
195 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_PGA_GAIN_POS, \
196 ADS114S0X_REGISTER_PGA_GAIN_LENGTH)
197 #define ADS114S0X_REGISTER_PGA_GAIN_SET(target, value) \
198 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_PGA_GAIN_POS, \
199 ADS114S0X_REGISTER_PGA_GAIN_LENGTH)
200 #define ADS114S0X_REGISTER_DATARATE_G_CHOP_LENGTH 1
201 #define ADS114S0X_REGISTER_DATARATE_G_CHOP_POS 7
202 #define ADS114S0X_REGISTER_DATARATE_G_CHOP_GET(value) \
203 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_DATARATE_G_CHOP_POS, \
204 ADS114S0X_REGISTER_DATARATE_G_CHOP_LENGTH)
205 #define ADS114S0X_REGISTER_DATARATE_G_CHOP_SET(target, value) \
206 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_DATARATE_G_CHOP_POS, \
207 ADS114S0X_REGISTER_DATARATE_G_CHOP_LENGTH)
208 #define ADS114S0X_REGISTER_DATARATE_CLK_LENGTH 1
209 #define ADS114S0X_REGISTER_DATARATE_CLK_POS 6
210 #define ADS114S0X_REGISTER_DATARATE_CLK_GET(value) \
211 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_DATARATE_CLK_POS, \
212 ADS114S0X_REGISTER_DATARATE_CLK_LENGTH)
213 #define ADS114S0X_REGISTER_DATARATE_CLK_SET(target, value) \
214 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_DATARATE_CLK_POS, \
215 ADS114S0X_REGISTER_DATARATE_CLK_LENGTH)
216 #define ADS114S0X_REGISTER_DATARATE_MODE_LENGTH 1
217 #define ADS114S0X_REGISTER_DATARATE_MODE_POS 5
218 #define ADS114S0X_REGISTER_DATARATE_MODE_GET(value) \
219 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_DATARATE_MODE_POS, \
220 ADS114S0X_REGISTER_DATARATE_MODE_LENGTH)
221 #define ADS114S0X_REGISTER_DATARATE_MODE_SET(target, value) \
222 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_DATARATE_MODE_POS, \
223 ADS114S0X_REGISTER_DATARATE_MODE_LENGTH)
224 #define ADS114S0X_REGISTER_DATARATE_FILTER_LENGTH 1
225 #define ADS114S0X_REGISTER_DATARATE_FILTER_POS 4
226 #define ADS114S0X_REGISTER_DATARATE_FILTER_GET(value) \
227 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_DATARATE_FILTER_POS, \
228 ADS114S0X_REGISTER_DATARATE_FILTER_LENGTH)
229 #define ADS114S0X_REGISTER_DATARATE_FILTER_SET(target, value) \
230 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_DATARATE_FILTER_POS, \
231 ADS114S0X_REGISTER_DATARATE_FILTER_LENGTH)
232 #define ADS114S0X_REGISTER_DATARATE_DR_LENGTH 4
233 #define ADS114S0X_REGISTER_DATARATE_DR_POS 0
234 #define ADS114S0X_REGISTER_DATARATE_DR_GET(value) \
235 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_DATARATE_DR_POS, \
236 ADS114S0X_REGISTER_DATARATE_DR_LENGTH)
237 #define ADS114S0X_REGISTER_DATARATE_DR_SET(target, value) \
238 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_DATARATE_DR_POS, \
239 ADS114S0X_REGISTER_DATARATE_DR_LENGTH)
240 #define ADS114S0X_REGISTER_REF_FL_REF_EN_LENGTH 2
241 #define ADS114S0X_REGISTER_REF_FL_REF_EN_POS 6
242 #define ADS114S0X_REGISTER_REF_FL_REF_EN_GET(value) \
243 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_REF_FL_REF_EN_POS, \
244 ADS114S0X_REGISTER_REF_FL_REF_EN_LENGTH)
245 #define ADS114S0X_REGISTER_REF_FL_REF_EN_SET(target, value) \
246 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_REF_FL_REF_EN_POS, \
247 ADS114S0X_REGISTER_REF_FL_REF_EN_LENGTH)
248 #define ADS114S0X_REGISTER_REF_NOT_REFP_BUF_LENGTH 1
249 #define ADS114S0X_REGISTER_REF_NOT_REFP_BUF_POS 5
250 #define ADS114S0X_REGISTER_REF_NOT_REFP_BUF_GET(value) \
251 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_REF_NOT_REFP_BUF_POS, \
252 ADS114S0X_REGISTER_REF_NOT_REFP_BUF_LENGTH)
253 #define ADS114S0X_REGISTER_REF_NOT_REFP_BUF_SET(target, value) \
254 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_REF_NOT_REFP_BUF_POS, \
255 ADS114S0X_REGISTER_REF_NOT_REFP_BUF_LENGTH)
256 #define ADS114S0X_REGISTER_REF_NOT_REFN_BUF_LENGTH 1
257 #define ADS114S0X_REGISTER_REF_NOT_REFN_BUF_POS 4
258 #define ADS114S0X_REGISTER_REF_NOT_REFN_BUF_GET(value) \
259 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_REF_NOT_REFN_BUF_POS, \
260 ADS114S0X_REGISTER_REF_NOT_REFN_BUF_LENGTH)
261 #define ADS114S0X_REGISTER_REF_NOT_REFN_BUF_SET(target, value) \
262 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_REF_NOT_REFN_BUF_POS, \
263 ADS114S0X_REGISTER_REF_NOT_REFN_BUF_LENGTH)
264 #define ADS114S0X_REGISTER_REF_REFSEL_LENGTH 2
265 #define ADS114S0X_REGISTER_REF_REFSEL_POS 2
266 #define ADS114S0X_REGISTER_REF_REFSEL_GET(value) \
267 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_REF_REFSEL_POS, \
268 ADS114S0X_REGISTER_REF_REFSEL_LENGTH)
269 #define ADS114S0X_REGISTER_REF_REFSEL_SET(target, value) \
270 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_REF_REFSEL_POS, \
271 ADS114S0X_REGISTER_REF_REFSEL_LENGTH)
272 #define ADS114S0X_REGISTER_REF_REFCON_LENGTH 2
273 #define ADS114S0X_REGISTER_REF_REFCON_POS 0
274 #define ADS114S0X_REGISTER_REF_REFCON_GET(value) \
275 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_REF_REFCON_POS, \
276 ADS114S0X_REGISTER_REF_REFCON_LENGTH)
277 #define ADS114S0X_REGISTER_REF_REFCON_SET(target, value) \
278 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_REF_REFCON_POS, \
279 ADS114S0X_REGISTER_REF_REFCON_LENGTH)
280 #define ADS114S0X_REGISTER_IDACMAG_FL_RAIL_EN_LENGTH 1
281 #define ADS114S0X_REGISTER_IDACMAG_FL_RAIL_EN_POS 7
282 #define ADS114S0X_REGISTER_IDACMAG_FL_RAIL_EN_GET(value) \
283 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_IDACMAG_FL_RAIL_EN_POS, \
284 ADS114S0X_REGISTER_IDACMAG_FL_RAIL_EN_LENGTH)
285 #define ADS114S0X_REGISTER_IDACMAG_FL_RAIL_EN_SET(target, value) \
286 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_IDACMAG_FL_RAIL_EN_POS, \
287 ADS114S0X_REGISTER_IDACMAG_FL_RAIL_EN_LENGTH)
288 #define ADS114S0X_REGISTER_IDACMAG_PSW_LENGTH 1
289 #define ADS114S0X_REGISTER_IDACMAG_PSW_POS 6
290 #define ADS114S0X_REGISTER_IDACMAG_PSW_GET(value) \
291 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_IDACMAG_PSW_POS, \
292 ADS114S0X_REGISTER_IDACMAG_PSW_LENGTH)
293 #define ADS114S0X_REGISTER_IDACMAG_PSW_SET(target, value) \
294 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_IDACMAG_PSW_POS, \
295 ADS114S0X_REGISTER_IDACMAG_PSW_LENGTH)
296 #define ADS114S0X_REGISTER_IDACMAG_IMAG_LENGTH 4
297 #define ADS114S0X_REGISTER_IDACMAG_IMAG_POS 0
298 #define ADS114S0X_REGISTER_IDACMAG_IMAG_GET(value) \
299 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_IDACMAG_IMAG_POS, \
300 ADS114S0X_REGISTER_IDACMAG_IMAG_LENGTH)
301 #define ADS114S0X_REGISTER_IDACMAG_IMAG_SET(target, value) \
302 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_IDACMAG_IMAG_POS, \
303 ADS114S0X_REGISTER_IDACMAG_IMAG_LENGTH)
304 #define ADS114S0X_REGISTER_IDACMUX_I2MUX_LENGTH 4
305 #define ADS114S0X_REGISTER_IDACMUX_I2MUX_POS 4
306 #define ADS114S0X_REGISTER_IDACMUX_I2MUX_GET(value) \
307 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_IDACMUX_I2MUX_POS, \
308 ADS114S0X_REGISTER_IDACMUX_I2MUX_LENGTH)
309 #define ADS114S0X_REGISTER_IDACMUX_I2MUX_SET(target, value) \
310 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_IDACMUX_I2MUX_POS, \
311 ADS114S0X_REGISTER_IDACMUX_I2MUX_LENGTH)
312 #define ADS114S0X_REGISTER_IDACMUX_I1MUX_LENGTH 4
313 #define ADS114S0X_REGISTER_IDACMUX_I1MUX_POS 0
314 #define ADS114S0X_REGISTER_IDACMUX_I1MUX_GET(value) \
315 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_IDACMUX_I1MUX_POS, \
316 ADS114S0X_REGISTER_IDACMUX_I1MUX_LENGTH)
317 #define ADS114S0X_REGISTER_IDACMUX_I1MUX_SET(target, value) \
318 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_IDACMUX_I1MUX_POS, \
319 ADS114S0X_REGISTER_IDACMUX_I1MUX_LENGTH)
320 #define ADS114S0X_REGISTER_GPIODAT_DIR_LENGTH 4
321 #define ADS114S0X_REGISTER_GPIODAT_DIR_POS 4
322 #define ADS114S0X_REGISTER_GPIODAT_DIR_GET(value) \
323 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_GPIODAT_DIR_POS, \
324 ADS114S0X_REGISTER_GPIODAT_DIR_LENGTH)
325 #define ADS114S0X_REGISTER_GPIODAT_DIR_SET(target, value) \
326 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_GPIODAT_DIR_POS, \
327 ADS114S0X_REGISTER_GPIODAT_DIR_LENGTH)
328 #define ADS114S0X_REGISTER_GPIODAT_DAT_LENGTH 4
329 #define ADS114S0X_REGISTER_GPIODAT_DAT_POS 0
330 #define ADS114S0X_REGISTER_GPIODAT_DAT_GET(value) \
331 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_GPIODAT_DAT_POS, \
332 ADS114S0X_REGISTER_GPIODAT_DAT_LENGTH)
333 #define ADS114S0X_REGISTER_GPIODAT_DAT_SET(target, value) \
334 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_GPIODAT_DAT_POS, \
335 ADS114S0X_REGISTER_GPIODAT_DAT_LENGTH)
336 #define ADS114S0X_REGISTER_GPIOCON_CON_LENGTH 4
337 #define ADS114S0X_REGISTER_GPIOCON_CON_POS 0
338 #define ADS114S0X_REGISTER_GPIOCON_CON_GET(value) \
339 ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_GPIOCON_CON_POS, \
340 ADS114S0X_REGISTER_GPIOCON_CON_LENGTH)
341 #define ADS114S0X_REGISTER_GPIOCON_CON_SET(target, value) \
342 ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_GPIOCON_CON_POS, \
343 ADS114S0X_REGISTER_GPIOCON_CON_LENGTH)
344
345 /*
346 * - AIN0 as positive input
347 * - AIN1 as negative input
348 */
349 #define ADS114S0X_REGISTER_INPMUX_SET_DEFAULTS(target) \
350 ADS114S0X_REGISTER_INPMUX_MUXP_SET(target, 0b0000); \
351 ADS114S0X_REGISTER_INPMUX_MUXN_SET(target, 0b0001)
352 /*
353 * - disable reference monitor
354 * - enable positive reference buffer
355 * - disable negative reference buffer
356 * - use internal reference
357 * - enable internal voltage reference
358 */
359 #define ADS114S0X_REGISTER_REF_SET_DEFAULTS(target) \
360 ADS114S0X_REGISTER_REF_FL_REF_EN_SET(target, 0b00); \
361 ADS114S0X_REGISTER_REF_NOT_REFP_BUF_SET(target, 0b0); \
362 ADS114S0X_REGISTER_REF_NOT_REFN_BUF_SET(target, 0b1); \
363 ADS114S0X_REGISTER_REF_REFSEL_SET(target, 0b10); \
364 ADS114S0X_REGISTER_REF_REFCON_SET(target, 0b01)
365 /*
366 * - disable global chop
367 * - use internal oscillator
368 * - single shot conversion mode
369 * - low latency filter
370 * - 20 samples per second
371 */
372 #define ADS114S0X_REGISTER_DATARATE_SET_DEFAULTS(target) \
373 ADS114S0X_REGISTER_DATARATE_G_CHOP_SET(target, 0b0); \
374 ADS114S0X_REGISTER_DATARATE_CLK_SET(target, 0b0); \
375 ADS114S0X_REGISTER_DATARATE_MODE_SET(target, 0b1); \
376 ADS114S0X_REGISTER_DATARATE_FILTER_SET(target, 0b1); \
377 ADS114S0X_REGISTER_DATARATE_DR_SET(target, 0b0100)
378 /*
379 * - delay of 14*t_mod
380 * - disable gain
381 * - gain 1
382 */
383 #define ADS114S0X_REGISTER_PGA_SET_DEFAULTS(target) \
384 ADS114S0X_REGISTER_PGA_DELAY_SET(target, 0b000); \
385 ADS114S0X_REGISTER_PGA_PGA_EN_SET(target, 0b00); \
386 ADS114S0X_REGISTER_PGA_GAIN_SET(target, 0b000)
387 /*
388 * - disable PGA output rail flag
389 * - low-side power switch
390 * - IDAC off
391 */
392 #define ADS114S0X_REGISTER_IDACMAG_SET_DEFAULTS(target) \
393 ADS114S0X_REGISTER_IDACMAG_FL_RAIL_EN_SET(target, 0b0); \
394 ADS114S0X_REGISTER_IDACMAG_PSW_SET(target, 0b0); \
395 ADS114S0X_REGISTER_IDACMAG_IMAG_SET(target, 0b0000)
396 /*
397 * - disconnect IDAC1
398 * - disconnect IDAC2
399 */
400 #define ADS114S0X_REGISTER_IDACMUX_SET_DEFAULTS(target) \
401 ADS114S0X_REGISTER_IDACMUX_I1MUX_SET(target, 0b1111); \
402 ADS114S0X_REGISTER_IDACMUX_I2MUX_SET(target, 0b1111)
403
404 struct ads114s0x_config {
405 struct spi_dt_spec bus;
406 #if CONFIG_ADC_ASYNC
407 k_thread_stack_t *stack;
408 #endif
409 const struct gpio_dt_spec gpio_reset;
410 const struct gpio_dt_spec gpio_data_ready;
411 const struct gpio_dt_spec gpio_start_sync;
412 int idac_current;
413 };
414
415 struct ads114s0x_data {
416 struct adc_context ctx;
417 #if CONFIG_ADC_ASYNC
418 struct k_thread thread;
419 #endif /* CONFIG_ADC_ASYNC */
420 struct gpio_callback callback_data_ready;
421 struct k_sem data_ready_signal;
422 struct k_sem acquire_signal;
423 int16_t *buffer;
424 int16_t *buffer_ptr;
425 #if CONFIG_ADC_ADS114S0X_GPIO
426 struct k_mutex gpio_lock;
427 uint8_t gpio_enabled; /* one bit per GPIO, 1 = enabled */
428 uint8_t gpio_direction; /* one bit per GPIO, 1 = input */
429 uint8_t gpio_value; /* one bit per GPIO, 1 = high */
430 #endif /* CONFIG_ADC_ADS114S0X_GPIO */
431 };
432
ads114s0x_data_ready_handler(const struct device * dev,struct gpio_callback * gpio_cb,uint32_t pins)433 static void ads114s0x_data_ready_handler(const struct device *dev, struct gpio_callback *gpio_cb,
434 uint32_t pins)
435 {
436 ARG_UNUSED(dev);
437 ARG_UNUSED(pins);
438
439 struct ads114s0x_data *data =
440 CONTAINER_OF(gpio_cb, struct ads114s0x_data, callback_data_ready);
441
442 k_sem_give(&data->data_ready_signal);
443 }
444
ads114s0x_read_register(const struct device * dev,enum ads114s0x_register register_address,uint8_t * value)445 static int ads114s0x_read_register(const struct device *dev,
446 enum ads114s0x_register register_address, uint8_t *value)
447 {
448 const struct ads114s0x_config *config = dev->config;
449 uint8_t buffer_tx[3];
450 uint8_t buffer_rx[ARRAY_SIZE(buffer_tx)];
451 const struct spi_buf tx_buf[] = {{
452 .buf = buffer_tx,
453 .len = ARRAY_SIZE(buffer_tx),
454 }};
455 const struct spi_buf rx_buf[] = {{
456 .buf = buffer_rx,
457 .len = ARRAY_SIZE(buffer_rx),
458 }};
459 const struct spi_buf_set tx = {
460 .buffers = tx_buf,
461 .count = ARRAY_SIZE(tx_buf),
462 };
463 const struct spi_buf_set rx = {
464 .buffers = rx_buf,
465 .count = ARRAY_SIZE(rx_buf),
466 };
467
468 buffer_tx[0] = ((uint8_t)ADS114S0X_COMMAND_RREG) | ((uint8_t)register_address);
469 /* read one register */
470 buffer_tx[1] = 0x00;
471
472 int result = spi_transceive_dt(&config->bus, &tx, &rx);
473
474 if (result != 0) {
475 LOG_ERR("%s: spi_transceive failed with error %i", dev->name, result);
476 return result;
477 }
478
479 *value = buffer_rx[2];
480 LOG_DBG("%s: read from register 0x%02X value 0x%02X", dev->name, register_address, *value);
481
482 return 0;
483 }
484
ads114s0x_write_register(const struct device * dev,enum ads114s0x_register register_address,uint8_t value)485 static int ads114s0x_write_register(const struct device *dev,
486 enum ads114s0x_register register_address, uint8_t value)
487 {
488 const struct ads114s0x_config *config = dev->config;
489 uint8_t buffer_tx[3];
490 const struct spi_buf tx_buf[] = {{
491 .buf = buffer_tx,
492 .len = ARRAY_SIZE(buffer_tx),
493 }};
494 const struct spi_buf_set tx = {
495 .buffers = tx_buf,
496 .count = ARRAY_SIZE(tx_buf),
497 };
498
499 buffer_tx[0] = ((uint8_t)ADS114S0X_COMMAND_WREG) | ((uint8_t)register_address);
500 /* write one register */
501 buffer_tx[1] = 0x00;
502 buffer_tx[2] = value;
503
504 LOG_DBG("%s: writing to register 0x%02X value 0x%02X", dev->name, register_address, value);
505 int result = spi_write_dt(&config->bus, &tx);
506
507 if (result != 0) {
508 LOG_ERR("%s: spi_write failed with error %i", dev->name, result);
509 return result;
510 }
511
512 return 0;
513 }
514
ads114s0x_write_multiple_registers(const struct device * dev,enum ads114s0x_register * register_addresses,uint8_t * values,size_t count)515 static int ads114s0x_write_multiple_registers(const struct device *dev,
516 enum ads114s0x_register *register_addresses,
517 uint8_t *values, size_t count)
518 {
519 const struct ads114s0x_config *config = dev->config;
520 uint8_t buffer_tx[2];
521 const struct spi_buf tx_buf[] = {
522 {
523 .buf = buffer_tx,
524 .len = ARRAY_SIZE(buffer_tx),
525 },
526 {
527 .buf = values,
528 .len = count,
529 },
530 };
531 const struct spi_buf_set tx = {
532 .buffers = tx_buf,
533 .count = ARRAY_SIZE(tx_buf),
534 };
535
536 if (count == 0) {
537 LOG_WRN("%s: ignoring the command to write 0 registers", dev->name);
538 return -EINVAL;
539 }
540
541 buffer_tx[0] = ((uint8_t)ADS114S0X_COMMAND_WREG) | ((uint8_t)register_addresses[0]);
542 buffer_tx[1] = count - 1;
543
544 LOG_HEXDUMP_DBG(register_addresses, count, "writing to registers");
545 LOG_HEXDUMP_DBG(values, count, "values");
546
547 /* ensure that the register addresses are in the correct order */
548 for (size_t i = 1; i < count; ++i) {
549 __ASSERT(register_addresses[i - 1] + 1 == register_addresses[i],
550 "register addresses are not consecutive");
551 }
552
553 int result = spi_write_dt(&config->bus, &tx);
554
555 if (result != 0) {
556 LOG_ERR("%s: spi_write failed with error %i", dev->name, result);
557 return result;
558 }
559
560 return 0;
561 }
562
ads114s0x_send_command(const struct device * dev,enum ads114s0x_command command)563 static int ads114s0x_send_command(const struct device *dev, enum ads114s0x_command command)
564 {
565 const struct ads114s0x_config *config = dev->config;
566 uint8_t buffer_tx[1];
567 const struct spi_buf tx_buf[] = {{
568 .buf = buffer_tx,
569 .len = ARRAY_SIZE(buffer_tx),
570 }};
571 const struct spi_buf_set tx = {
572 .buffers = tx_buf,
573 .count = ARRAY_SIZE(tx_buf),
574 };
575
576 buffer_tx[0] = (uint8_t)command;
577
578 LOG_DBG("%s: sending command 0x%02X", dev->name, command);
579 int result = spi_write_dt(&config->bus, &tx);
580
581 if (result != 0) {
582 LOG_ERR("%s: spi_write failed with error %i", dev->name, result);
583 return result;
584 }
585
586 return 0;
587 }
588
ads114s0x_channel_setup(const struct device * dev,const struct adc_channel_cfg * channel_cfg)589 static int ads114s0x_channel_setup(const struct device *dev,
590 const struct adc_channel_cfg *channel_cfg)
591 {
592 const struct ads114s0x_config *config = dev->config;
593 uint8_t input_mux = 0;
594 uint8_t reference_control = 0;
595 uint8_t data_rate = 0;
596 uint8_t gain = 0;
597 uint8_t idac_magnitude = 0;
598 uint8_t idac_mux = 0;
599 uint8_t pin_selections[4];
600 size_t pin_selections_size;
601 int result;
602 enum ads114s0x_register register_addresses[6];
603 uint8_t values[ARRAY_SIZE(register_addresses)];
604 uint16_t acquisition_time_value = ADC_ACQ_TIME_VALUE(channel_cfg->acquisition_time);
605 uint16_t acquisition_time_unit = ADC_ACQ_TIME_UNIT(channel_cfg->acquisition_time);
606
607 ADS114S0X_REGISTER_INPMUX_SET_DEFAULTS(gain);
608 ADS114S0X_REGISTER_REF_SET_DEFAULTS(reference_control);
609 ADS114S0X_REGISTER_DATARATE_SET_DEFAULTS(data_rate);
610 ADS114S0X_REGISTER_PGA_SET_DEFAULTS(gain);
611 ADS114S0X_REGISTER_IDACMAG_SET_DEFAULTS(idac_magnitude);
612 ADS114S0X_REGISTER_IDACMUX_SET_DEFAULTS(idac_mux);
613
614 if (channel_cfg->channel_id != 0) {
615 LOG_ERR("%s: only one channel is supported", dev->name);
616 return -EINVAL;
617 }
618
619 /* The ADS114 uses samples per seconds units with the lowest being 2.5SPS
620 * and with acquisition_time only having 14b for time, this will not fit
621 * within here for microsecond units. Use Tick units and allow the user to
622 * specify the ODR directly.
623 */
624 if (channel_cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT &&
625 acquisition_time_unit != ADC_ACQ_TIME_TICKS) {
626 LOG_ERR("%s: invalid acquisition time %i", dev->name,
627 channel_cfg->acquisition_time);
628 return -EINVAL;
629 }
630
631 if (channel_cfg->acquisition_time == ADC_ACQ_TIME_DEFAULT) {
632 ADS114S0X_REGISTER_DATARATE_DR_SET(data_rate, ADS114S0X_CONFIG_DR_20);
633 } else {
634 ADS114S0X_REGISTER_DATARATE_DR_SET(data_rate, acquisition_time_value);
635 }
636
637 switch (channel_cfg->reference) {
638 case ADC_REF_INTERNAL:
639 /* disable negative reference buffer */
640 ADS114S0X_REGISTER_REF_NOT_REFN_BUF_SET(reference_control, 0b1);
641 /* disable positive reference buffer */
642 ADS114S0X_REGISTER_REF_NOT_REFP_BUF_SET(reference_control, 0b1);
643 /* use internal reference */
644 ADS114S0X_REGISTER_REF_REFSEL_SET(reference_control, 0b10);
645 break;
646 case ADC_REF_EXTERNAL0:
647 /* enable negative reference buffer */
648 ADS114S0X_REGISTER_REF_NOT_REFN_BUF_SET(reference_control, 0b0);
649 /* enable positive reference buffer */
650 ADS114S0X_REGISTER_REF_NOT_REFP_BUF_SET(reference_control, 0b0);
651 /* use external reference 0*/
652 ADS114S0X_REGISTER_REF_REFSEL_SET(reference_control, 0b00);
653 break;
654 case ADC_REF_EXTERNAL1:
655 /* enable negative reference buffer */
656 ADS114S0X_REGISTER_REF_NOT_REFN_BUF_SET(reference_control, 0b0);
657 /* enable positive reference buffer */
658 ADS114S0X_REGISTER_REF_NOT_REFP_BUF_SET(reference_control, 0b0);
659 /* use external reference 0*/
660 ADS114S0X_REGISTER_REF_REFSEL_SET(reference_control, 0b01);
661 break;
662 default:
663 LOG_ERR("%s: reference %i is not supported", dev->name, channel_cfg->reference);
664 return -EINVAL;
665 }
666
667 if (channel_cfg->differential) {
668 LOG_DBG("%s: configuring channel for a differential measurement from the pins (p, "
669 "n) (%i, %i)",
670 dev->name, channel_cfg->input_positive, channel_cfg->input_negative);
671 if (channel_cfg->input_positive >= ADS114S0X_INPUT_SELECTION_AINCOM) {
672 LOG_ERR("%s: positive channel input %i is invalid", dev->name,
673 channel_cfg->input_positive);
674 return -EINVAL;
675 }
676
677 if (channel_cfg->input_negative >= ADS114S0X_INPUT_SELECTION_AINCOM) {
678 LOG_ERR("%s: negative channel input %i is invalid", dev->name,
679 channel_cfg->input_negative);
680 return -EINVAL;
681 }
682
683 if (channel_cfg->input_positive == channel_cfg->input_negative) {
684 LOG_ERR("%s: negative and positive channel inputs must be different",
685 dev->name);
686 return -EINVAL;
687 }
688
689 ADS114S0X_REGISTER_INPMUX_MUXP_SET(input_mux, channel_cfg->input_positive);
690 ADS114S0X_REGISTER_INPMUX_MUXN_SET(input_mux, channel_cfg->input_negative);
691 pin_selections[0] = channel_cfg->input_positive;
692 pin_selections[1] = channel_cfg->input_negative;
693 } else {
694 LOG_DBG("%s: configuring channel for single ended measurement from input %i",
695 dev->name, channel_cfg->input_positive);
696 if (channel_cfg->input_positive >= ADS114S0X_INPUT_SELECTION_AINCOM) {
697 LOG_ERR("%s: channel input %i is invalid", dev->name,
698 channel_cfg->input_positive);
699 return -EINVAL;
700 }
701
702 ADS114S0X_REGISTER_INPMUX_MUXP_SET(input_mux, channel_cfg->input_positive);
703 ADS114S0X_REGISTER_INPMUX_MUXN_SET(input_mux, ADS114S0X_INPUT_SELECTION_AINCOM);
704 pin_selections[0] = channel_cfg->input_positive;
705 pin_selections[1] = ADS114S0X_INPUT_SELECTION_AINCOM;
706 }
707
708 switch (channel_cfg->gain) {
709 case ADC_GAIN_1:
710 /* set gain value */
711 ADS114S0X_REGISTER_PGA_GAIN_SET(gain, 0b000);
712 break;
713 case ADC_GAIN_2:
714 ADS114S0X_REGISTER_PGA_GAIN_SET(gain, 0b001);
715 break;
716 case ADC_GAIN_4:
717 ADS114S0X_REGISTER_PGA_GAIN_SET(gain, 0b010);
718 break;
719 case ADC_GAIN_8:
720 ADS114S0X_REGISTER_PGA_GAIN_SET(gain, 0b011);
721 break;
722 case ADC_GAIN_16:
723 ADS114S0X_REGISTER_PGA_GAIN_SET(gain, 0b100);
724 break;
725 case ADC_GAIN_32:
726 ADS114S0X_REGISTER_PGA_GAIN_SET(gain, 0b101);
727 break;
728 case ADC_GAIN_64:
729 ADS114S0X_REGISTER_PGA_GAIN_SET(gain, 0b110);
730 break;
731 case ADC_GAIN_128:
732 ADS114S0X_REGISTER_PGA_GAIN_SET(gain, 0b111);
733 break;
734 default:
735 LOG_ERR("%s: gain value %i not supported", dev->name, channel_cfg->gain);
736 return -EINVAL;
737 }
738
739 if (channel_cfg->gain != ADC_GAIN_1) {
740 /* enable gain */
741 ADS114S0X_REGISTER_PGA_PGA_EN_SET(gain, 0b01);
742 }
743
744 switch (config->idac_current) {
745 case 0:
746 ADS114S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0000);
747 break;
748 case 10:
749 ADS114S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0001);
750 break;
751 case 50:
752 ADS114S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0010);
753 break;
754 case 100:
755 ADS114S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0011);
756 break;
757 case 250:
758 ADS114S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0100);
759 break;
760 case 500:
761 ADS114S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0101);
762 break;
763 case 750:
764 ADS114S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0110);
765 break;
766 case 1000:
767 ADS114S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0111);
768 break;
769 case 1500:
770 ADS114S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b1000);
771 break;
772 case 2000:
773 ADS114S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b1001);
774 break;
775 default:
776 LOG_ERR("%s: IDAC magnitude %i not supported", dev->name, config->idac_current);
777 return -EINVAL;
778 }
779
780 if (channel_cfg->current_source_pin_set) {
781 LOG_DBG("%s: current source pin set to %i and %i", dev->name,
782 channel_cfg->current_source_pin[0], channel_cfg->current_source_pin[1]);
783 if (channel_cfg->current_source_pin[0] > 0b1111) {
784 LOG_ERR("%s: invalid selection %i for I1MUX", dev->name,
785 channel_cfg->current_source_pin[0]);
786 return -EINVAL;
787 }
788
789 if (channel_cfg->current_source_pin[1] > 0b1111) {
790 LOG_ERR("%s: invalid selection %i for I2MUX", dev->name,
791 channel_cfg->current_source_pin[1]);
792 return -EINVAL;
793 }
794
795 ADS114S0X_REGISTER_IDACMUX_I1MUX_SET(idac_mux, channel_cfg->current_source_pin[0]);
796 ADS114S0X_REGISTER_IDACMUX_I2MUX_SET(idac_mux, channel_cfg->current_source_pin[1]);
797 pin_selections[2] = channel_cfg->current_source_pin[0];
798 pin_selections[3] = channel_cfg->current_source_pin[1];
799 pin_selections_size = 4;
800 } else {
801 LOG_DBG("%s: current source pins not set", dev->name);
802 pin_selections_size = 2;
803 }
804
805 for (size_t i = 0; i < pin_selections_size; ++i) {
806 if (pin_selections[i] > ADS114S0X_INPUT_SELECTION_AINCOM) {
807 continue;
808 }
809
810 for (size_t j = i + 1; j < pin_selections_size; ++j) {
811 if (pin_selections[j] > ADS114S0X_INPUT_SELECTION_AINCOM) {
812 continue;
813 }
814
815 if (pin_selections[i] == pin_selections[j]) {
816 LOG_ERR("%s: pins for inputs and current sources must be different",
817 dev->name);
818 return -EINVAL;
819 }
820 }
821 }
822
823 register_addresses[0] = ADS114S0X_REGISTER_INPMUX;
824 register_addresses[1] = ADS114S0X_REGISTER_PGA;
825 register_addresses[2] = ADS114S0X_REGISTER_DATARATE;
826 register_addresses[3] = ADS114S0X_REGISTER_REF;
827 register_addresses[4] = ADS114S0X_REGISTER_IDACMAG;
828 register_addresses[5] = ADS114S0X_REGISTER_IDACMUX;
829 BUILD_ASSERT(ARRAY_SIZE(register_addresses) == 6);
830 values[0] = input_mux;
831 values[1] = gain;
832 values[2] = data_rate;
833 values[3] = reference_control;
834 values[4] = idac_magnitude;
835 values[5] = idac_mux;
836 BUILD_ASSERT(ARRAY_SIZE(values) == 6);
837
838 result = ads114s0x_write_multiple_registers(dev, register_addresses, values,
839 ARRAY_SIZE(values));
840
841 if (result != 0) {
842 LOG_ERR("%s: unable to configure registers", dev->name);
843 return result;
844 }
845
846 return 0;
847 }
848
ads114s0x_validate_buffer_size(const struct adc_sequence * sequence)849 static int ads114s0x_validate_buffer_size(const struct adc_sequence *sequence)
850 {
851 size_t needed = sizeof(int16_t);
852
853 if (sequence->options) {
854 needed *= (1 + sequence->options->extra_samplings);
855 }
856
857 if (sequence->buffer_size < needed) {
858 return -ENOMEM;
859 }
860
861 return 0;
862 }
863
ads114s0x_validate_sequence(const struct device * dev,const struct adc_sequence * sequence)864 static int ads114s0x_validate_sequence(const struct device *dev,
865 const struct adc_sequence *sequence)
866 {
867 if (sequence->resolution != ADS114S0X_RESOLUTION) {
868 LOG_ERR("%s: invalid resolution", dev->name);
869 return -EINVAL;
870 }
871
872 if (sequence->channels != BIT(0)) {
873 LOG_ERR("%s: invalid channel", dev->name);
874 return -EINVAL;
875 }
876
877 if (sequence->oversampling) {
878 LOG_ERR("%s: oversampling is not supported", dev->name);
879 return -EINVAL;
880 }
881
882 return ads114s0x_validate_buffer_size(sequence);
883 }
884
adc_context_update_buffer_pointer(struct adc_context * ctx,bool repeat_sampling)885 static void adc_context_update_buffer_pointer(struct adc_context *ctx, bool repeat_sampling)
886 {
887 struct ads114s0x_data *data = CONTAINER_OF(ctx, struct ads114s0x_data, ctx);
888
889 if (repeat_sampling) {
890 data->buffer = data->buffer_ptr;
891 }
892 }
893
adc_context_start_sampling(struct adc_context * ctx)894 static void adc_context_start_sampling(struct adc_context *ctx)
895 {
896 struct ads114s0x_data *data = CONTAINER_OF(ctx, struct ads114s0x_data, ctx);
897
898 data->buffer_ptr = data->buffer;
899 k_sem_give(&data->acquire_signal);
900 }
901
ads114s0x_adc_start_read(const struct device * dev,const struct adc_sequence * sequence,bool wait)902 static int ads114s0x_adc_start_read(const struct device *dev, const struct adc_sequence *sequence,
903 bool wait)
904 {
905 int result;
906 struct ads114s0x_data *data = dev->data;
907
908 result = ads114s0x_validate_sequence(dev, sequence);
909
910 if (result != 0) {
911 LOG_ERR("%s: sequence validation failed", dev->name);
912 return result;
913 }
914
915 data->buffer = sequence->buffer;
916
917 adc_context_start_read(&data->ctx, sequence);
918
919 if (wait) {
920 result = adc_context_wait_for_completion(&data->ctx);
921 }
922
923 return result;
924 }
925
ads114s0x_send_start_read(const struct device * dev)926 static int ads114s0x_send_start_read(const struct device *dev)
927 {
928 const struct ads114s0x_config *config = dev->config;
929 int result;
930
931 if (config->gpio_start_sync.port == 0) {
932 result = ads114s0x_send_command(dev, ADS114S0X_COMMAND_START);
933 if (result != 0) {
934 LOG_ERR("%s: unable to send START/SYNC command", dev->name);
935 return result;
936 }
937 } else {
938 result = gpio_pin_set_dt(&config->gpio_start_sync, 1);
939
940 if (result != 0) {
941 LOG_ERR("%s: unable to start ADC operation", dev->name);
942 return result;
943 }
944
945 k_sleep(K_USEC(ADS114S0X_START_SYNC_PULSE_DURATION_IN_US +
946 ADS114S0X_SETUP_TIME_IN_US));
947
948 result = gpio_pin_set_dt(&config->gpio_start_sync, 0);
949
950 if (result != 0) {
951 LOG_ERR("%s: unable to start ADC operation", dev->name);
952 return result;
953 }
954 }
955
956 return 0;
957 }
958
ads114s0x_wait_data_ready(const struct device * dev)959 static int ads114s0x_wait_data_ready(const struct device *dev)
960 {
961 struct ads114s0x_data *data = dev->data;
962
963 return k_sem_take(&data->data_ready_signal, ADC_CONTEXT_WAIT_FOR_COMPLETION_TIMEOUT);
964 }
965
ads114s0x_read_sample(const struct device * dev,uint16_t * buffer)966 static int ads114s0x_read_sample(const struct device *dev, uint16_t *buffer)
967 {
968 const struct ads114s0x_config *config = dev->config;
969 uint8_t buffer_tx[3];
970 uint8_t buffer_rx[ARRAY_SIZE(buffer_tx)];
971 const struct spi_buf tx_buf[] = {{
972 .buf = buffer_tx,
973 .len = ARRAY_SIZE(buffer_tx),
974 }};
975 const struct spi_buf rx_buf[] = {{
976 .buf = buffer_rx,
977 .len = ARRAY_SIZE(buffer_rx),
978 }};
979 const struct spi_buf_set tx = {
980 .buffers = tx_buf,
981 .count = ARRAY_SIZE(tx_buf),
982 };
983 const struct spi_buf_set rx = {
984 .buffers = rx_buf,
985 .count = ARRAY_SIZE(rx_buf),
986 };
987
988 buffer_tx[0] = (uint8_t)ADS114S0X_COMMAND_RDATA;
989
990 int result = spi_transceive_dt(&config->bus, &tx, &rx);
991
992 if (result != 0) {
993 LOG_ERR("%s: spi_transceive failed with error %i", dev->name, result);
994 return result;
995 }
996
997 *buffer = sys_get_be16(buffer_rx + 1);
998 LOG_DBG("%s: read ADC sample %i", dev->name, *buffer);
999
1000 return 0;
1001 }
1002
ads114s0x_adc_perform_read(const struct device * dev)1003 static int ads114s0x_adc_perform_read(const struct device *dev)
1004 {
1005 int result;
1006 struct ads114s0x_data *data = dev->data;
1007
1008 k_sem_take(&data->acquire_signal, K_FOREVER);
1009
1010 result = ads114s0x_send_start_read(dev);
1011 if (result != 0) {
1012 LOG_ERR("%s: unable to start ADC conversion", dev->name);
1013 adc_context_complete(&data->ctx, result);
1014 return result;
1015 }
1016
1017 result = ads114s0x_wait_data_ready(dev);
1018 if (result != 0) {
1019 LOG_ERR("%s: waiting for data to be ready failed", dev->name);
1020 adc_context_complete(&data->ctx, result);
1021 return result;
1022 }
1023
1024 result = ads114s0x_read_sample(dev, data->buffer);
1025 if (result != 0) {
1026 LOG_ERR("%s: reading sample failed", dev->name);
1027 adc_context_complete(&data->ctx, result);
1028 return result;
1029 }
1030
1031 data->buffer++;
1032
1033 adc_context_on_sampling_done(&data->ctx, dev);
1034
1035 return result;
1036 }
1037
1038 #if CONFIG_ADC_ASYNC
ads114s0x_adc_read_async(const struct device * dev,const struct adc_sequence * sequence,struct k_poll_signal * async)1039 static int ads114s0x_adc_read_async(const struct device *dev, const struct adc_sequence *sequence,
1040 struct k_poll_signal *async)
1041 {
1042 int result;
1043 struct ads114s0x_data *data = dev->data;
1044
1045 adc_context_lock(&data->ctx, true, async);
1046 result = ads114s0x_adc_start_read(dev, sequence, true);
1047 adc_context_release(&data->ctx, result);
1048
1049 return result;
1050 }
1051
ads114s0x_read(const struct device * dev,const struct adc_sequence * sequence)1052 static int ads114s0x_read(const struct device *dev, const struct adc_sequence *sequence)
1053 {
1054 int result;
1055 struct ads114s0x_data *data = dev->data;
1056
1057 adc_context_lock(&data->ctx, false, NULL);
1058 result = ads114s0x_adc_start_read(dev, sequence, true);
1059 adc_context_release(&data->ctx, result);
1060
1061 return result;
1062 }
1063
1064 #else
ads114s0x_read(const struct device * dev,const struct adc_sequence * sequence)1065 static int ads114s0x_read(const struct device *dev, const struct adc_sequence *sequence)
1066 {
1067 int result;
1068 struct ads114s0x_data *data = dev->data;
1069
1070 adc_context_lock(&data->ctx, false, NULL);
1071 result = ads114s0x_adc_start_read(dev, sequence, false);
1072
1073 while (result == 0 && k_sem_take(&data->ctx.sync, K_NO_WAIT) != 0) {
1074 result = ads114s0x_adc_perform_read(dev);
1075 }
1076
1077 adc_context_release(&data->ctx, result);
1078 return result;
1079 }
1080 #endif
1081
1082 #if CONFIG_ADC_ASYNC
ads114s0x_acquisition_thread(void * p1,void * p2,void * p3)1083 static void ads114s0x_acquisition_thread(void *p1, void *p2, void *p3)
1084 {
1085 ARG_UNUSED(p2);
1086 ARG_UNUSED(p3);
1087
1088 const struct device *dev = p1;
1089 while (true) {
1090 ads114s0x_adc_perform_read(dev);
1091 }
1092 }
1093 #endif
1094
1095 #ifdef CONFIG_ADC_ADS114S0X_GPIO
ads114s0x_gpio_write_config(const struct device * dev)1096 static int ads114s0x_gpio_write_config(const struct device *dev)
1097 {
1098 struct ads114s0x_data *data = dev->data;
1099 enum ads114s0x_register register_addresses[2];
1100 uint8_t register_values[ARRAY_SIZE(register_addresses)];
1101 uint8_t gpio_dat = 0;
1102 uint8_t gpio_con = 0;
1103
1104 ADS114S0X_REGISTER_GPIOCON_CON_SET(gpio_con, data->gpio_enabled);
1105 ADS114S0X_REGISTER_GPIODAT_DAT_SET(gpio_dat, data->gpio_value);
1106 ADS114S0X_REGISTER_GPIODAT_DIR_SET(gpio_dat, data->gpio_direction);
1107
1108 register_values[0] = gpio_dat;
1109 register_values[1] = gpio_con;
1110 register_addresses[0] = ADS114S0X_REGISTER_GPIODAT;
1111 register_addresses[1] = ADS114S0X_REGISTER_GPIOCON;
1112 return ads114s0x_write_multiple_registers(dev, register_addresses, register_values,
1113 ARRAY_SIZE(register_values));
1114 }
1115
ads114s0x_gpio_write_value(const struct device * dev)1116 static int ads114s0x_gpio_write_value(const struct device *dev)
1117 {
1118 struct ads114s0x_data *data = dev->data;
1119 uint8_t gpio_dat = 0;
1120
1121 ADS114S0X_REGISTER_GPIODAT_DAT_SET(gpio_dat, data->gpio_value);
1122 ADS114S0X_REGISTER_GPIODAT_DIR_SET(gpio_dat, data->gpio_direction);
1123
1124 return ads114s0x_write_register(dev, ADS114S0X_REGISTER_GPIODAT, gpio_dat);
1125 }
1126
ads114s0x_gpio_set_output(const struct device * dev,uint8_t pin,bool initial_value)1127 int ads114s0x_gpio_set_output(const struct device *dev, uint8_t pin, bool initial_value)
1128 {
1129 struct ads114s0x_data *data = dev->data;
1130 int result = 0;
1131
1132 if (pin > ADS114S0X_GPIO_MAX) {
1133 LOG_ERR("%s: invalid pin %i", dev->name, pin);
1134 return -EINVAL;
1135 }
1136
1137 k_mutex_lock(&data->gpio_lock, K_FOREVER);
1138
1139 data->gpio_enabled |= BIT(pin);
1140 data->gpio_direction &= ~BIT(pin);
1141
1142 if (initial_value) {
1143 data->gpio_value |= BIT(pin);
1144 } else {
1145 data->gpio_value &= ~BIT(pin);
1146 }
1147
1148 result = ads114s0x_gpio_write_config(dev);
1149
1150 k_mutex_unlock(&data->gpio_lock);
1151
1152 return result;
1153 }
1154
ads114s0x_gpio_set_input(const struct device * dev,uint8_t pin)1155 int ads114s0x_gpio_set_input(const struct device *dev, uint8_t pin)
1156 {
1157 struct ads114s0x_data *data = dev->data;
1158 int result = 0;
1159
1160 if (pin > ADS114S0X_GPIO_MAX) {
1161 LOG_ERR("%s: invalid pin %i", dev->name, pin);
1162 return -EINVAL;
1163 }
1164
1165 k_mutex_lock(&data->gpio_lock, K_FOREVER);
1166
1167 data->gpio_enabled |= BIT(pin);
1168 data->gpio_direction |= BIT(pin);
1169 data->gpio_value &= ~BIT(pin);
1170
1171 result = ads114s0x_gpio_write_config(dev);
1172
1173 k_mutex_unlock(&data->gpio_lock);
1174
1175 return result;
1176 }
1177
ads114s0x_gpio_deconfigure(const struct device * dev,uint8_t pin)1178 int ads114s0x_gpio_deconfigure(const struct device *dev, uint8_t pin)
1179 {
1180 struct ads114s0x_data *data = dev->data;
1181 int result = 0;
1182
1183 if (pin > ADS114S0X_GPIO_MAX) {
1184 LOG_ERR("%s: invalid pin %i", dev->name, pin);
1185 return -EINVAL;
1186 }
1187
1188 k_mutex_lock(&data->gpio_lock, K_FOREVER);
1189
1190 data->gpio_enabled &= ~BIT(pin);
1191 data->gpio_direction |= BIT(pin);
1192 data->gpio_value &= ~BIT(pin);
1193
1194 result = ads114s0x_gpio_write_config(dev);
1195
1196 k_mutex_unlock(&data->gpio_lock);
1197
1198 return result;
1199 }
1200
ads114s0x_gpio_set_pin_value(const struct device * dev,uint8_t pin,bool value)1201 int ads114s0x_gpio_set_pin_value(const struct device *dev, uint8_t pin, bool value)
1202 {
1203 struct ads114s0x_data *data = dev->data;
1204 int result = 0;
1205
1206 if (pin > ADS114S0X_GPIO_MAX) {
1207 LOG_ERR("%s: invalid pin %i", dev->name, pin);
1208 return -EINVAL;
1209 }
1210
1211 k_mutex_lock(&data->gpio_lock, K_FOREVER);
1212
1213 if ((BIT(pin) & data->gpio_enabled) == 0) {
1214 LOG_ERR("%s: gpio pin %i not configured", dev->name, pin);
1215 result = -EINVAL;
1216 } else if ((BIT(pin) & data->gpio_direction) != 0) {
1217 LOG_ERR("%s: gpio pin %i not configured as output", dev->name, pin);
1218 result = -EINVAL;
1219 } else {
1220 data->gpio_value |= BIT(pin);
1221
1222 result = ads114s0x_gpio_write_value(dev);
1223 }
1224
1225 k_mutex_unlock(&data->gpio_lock);
1226
1227 return result;
1228 }
1229
ads114s0x_gpio_get_pin_value(const struct device * dev,uint8_t pin,bool * value)1230 int ads114s0x_gpio_get_pin_value(const struct device *dev, uint8_t pin, bool *value)
1231 {
1232 struct ads114s0x_data *data = dev->data;
1233 int result = 0;
1234 uint8_t gpio_dat;
1235
1236 if (pin > ADS114S0X_GPIO_MAX) {
1237 LOG_ERR("%s: invalid pin %i", dev->name, pin);
1238 return -EINVAL;
1239 }
1240
1241 k_mutex_lock(&data->gpio_lock, K_FOREVER);
1242
1243 if ((BIT(pin) & data->gpio_enabled) == 0) {
1244 LOG_ERR("%s: gpio pin %i not configured", dev->name, pin);
1245 result = -EINVAL;
1246 } else if ((BIT(pin) & data->gpio_direction) == 0) {
1247 LOG_ERR("%s: gpio pin %i not configured as input", dev->name, pin);
1248 result = -EINVAL;
1249 } else {
1250 result = ads114s0x_read_register(dev, ADS114S0X_REGISTER_GPIODAT, &gpio_dat);
1251 data->gpio_value = ADS114S0X_REGISTER_GPIODAT_DAT_GET(gpio_dat);
1252 *value = (BIT(pin) & data->gpio_value) != 0;
1253 }
1254
1255 k_mutex_unlock(&data->gpio_lock);
1256
1257 return result;
1258 }
1259
ads114s0x_gpio_port_get_raw(const struct device * dev,gpio_port_value_t * value)1260 int ads114s0x_gpio_port_get_raw(const struct device *dev, gpio_port_value_t *value)
1261 {
1262 struct ads114s0x_data *data = dev->data;
1263 int result = 0;
1264 uint8_t gpio_dat;
1265
1266 k_mutex_lock(&data->gpio_lock, K_FOREVER);
1267
1268 result = ads114s0x_read_register(dev, ADS114S0X_REGISTER_GPIODAT, &gpio_dat);
1269 data->gpio_value = ADS114S0X_REGISTER_GPIODAT_DAT_GET(gpio_dat);
1270 *value = data->gpio_value;
1271
1272 k_mutex_unlock(&data->gpio_lock);
1273
1274 return result;
1275 }
1276
ads114s0x_gpio_port_set_masked_raw(const struct device * dev,gpio_port_pins_t mask,gpio_port_value_t value)1277 int ads114s0x_gpio_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask,
1278 gpio_port_value_t value)
1279 {
1280 struct ads114s0x_data *data = dev->data;
1281 int result = 0;
1282
1283 k_mutex_lock(&data->gpio_lock, K_FOREVER);
1284
1285 data->gpio_value = ((data->gpio_value & ~mask) | (mask & value)) & data->gpio_enabled &
1286 ~data->gpio_direction;
1287 result = ads114s0x_gpio_write_value(dev);
1288
1289 k_mutex_unlock(&data->gpio_lock);
1290
1291 return result;
1292 }
1293
ads114s0x_gpio_port_toggle_bits(const struct device * dev,gpio_port_pins_t pins)1294 int ads114s0x_gpio_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins)
1295 {
1296 struct ads114s0x_data *data = dev->data;
1297 int result = 0;
1298
1299 k_mutex_lock(&data->gpio_lock, K_FOREVER);
1300
1301 data->gpio_value = (data->gpio_value ^ pins) & data->gpio_enabled & ~data->gpio_direction;
1302 result = ads114s0x_gpio_write_value(dev);
1303
1304 k_mutex_unlock(&data->gpio_lock);
1305
1306 return result;
1307 }
1308
1309 #endif /* CONFIG_ADC_ADS114S0X_GPIO */
1310
ads114s0x_init(const struct device * dev)1311 static int ads114s0x_init(const struct device *dev)
1312 {
1313 uint8_t status = 0;
1314 uint8_t reference_control = 0;
1315 uint8_t reference_control_read;
1316 int result;
1317 const struct ads114s0x_config *config = dev->config;
1318 struct ads114s0x_data *data = dev->data;
1319
1320 adc_context_init(&data->ctx);
1321
1322 k_sem_init(&data->data_ready_signal, 0, 1);
1323 k_sem_init(&data->acquire_signal, 0, 1);
1324
1325 #ifdef CONFIG_ADC_ADS114S0X_GPIO
1326 k_mutex_init(&data->gpio_lock);
1327 #endif /* CONFIG_ADC_ADS114S0X_GPIO */
1328
1329 if (!spi_is_ready_dt(&config->bus)) {
1330 LOG_ERR("%s: SPI device is not ready", dev->name);
1331 return -ENODEV;
1332 }
1333
1334 if (config->gpio_reset.port != NULL) {
1335 result = gpio_pin_configure_dt(&config->gpio_reset, GPIO_OUTPUT_ACTIVE);
1336 if (result != 0) {
1337 LOG_ERR("%s: failed to initialize GPIO for reset", dev->name);
1338 return result;
1339 }
1340 }
1341
1342 if (config->gpio_start_sync.port != NULL) {
1343 result = gpio_pin_configure_dt(&config->gpio_start_sync, GPIO_OUTPUT_INACTIVE);
1344 if (result != 0) {
1345 LOG_ERR("%s: failed to initialize GPIO for start/sync", dev->name);
1346 return result;
1347 }
1348 }
1349
1350 result = gpio_pin_configure_dt(&config->gpio_data_ready, GPIO_INPUT);
1351 if (result != 0) {
1352 LOG_ERR("%s: failed to initialize GPIO for data ready", dev->name);
1353 return result;
1354 }
1355
1356 result = gpio_pin_interrupt_configure_dt(&config->gpio_data_ready, GPIO_INT_EDGE_TO_ACTIVE);
1357 if (result != 0) {
1358 LOG_ERR("%s: failed to configure data ready interrupt", dev->name);
1359 return -EIO;
1360 }
1361
1362 gpio_init_callback(&data->callback_data_ready, ads114s0x_data_ready_handler,
1363 BIT(config->gpio_data_ready.pin));
1364 result = gpio_add_callback(config->gpio_data_ready.port, &data->callback_data_ready);
1365 if (result != 0) {
1366 LOG_ERR("%s: failed to add data ready callback", dev->name);
1367 return -EIO;
1368 }
1369
1370 #if CONFIG_ADC_ASYNC
1371 k_tid_t tid = k_thread_create(&data->thread, config->stack,
1372 CONFIG_ADC_ADS114S0X_ACQUISITION_THREAD_STACK_SIZE,
1373 ads114s0x_acquisition_thread, (void *)dev, NULL, NULL,
1374 CONFIG_ADC_ADS114S0X_ASYNC_THREAD_INIT_PRIO, 0, K_NO_WAIT);
1375 k_thread_name_set(tid, "adc_ads114s0x");
1376 #endif
1377
1378 k_busy_wait(ADS114S0X_POWER_ON_RESET_TIME_IN_US);
1379
1380 if (config->gpio_reset.port == NULL) {
1381 result = ads114s0x_send_command(dev, ADS114S0X_COMMAND_RESET);
1382 if (result != 0) {
1383 LOG_ERR("%s: unable to send RESET command", dev->name);
1384 return result;
1385 }
1386 } else {
1387 k_busy_wait(ADS114S0X_RESET_LOW_TIME_IN_US);
1388 gpio_pin_set_dt(&config->gpio_reset, 0);
1389 }
1390
1391 k_busy_wait(ADS114S0X_RESET_DELAY_TIME_IN_US);
1392
1393 result = ads114s0x_read_register(dev, ADS114S0X_REGISTER_STATUS, &status);
1394 if (result != 0) {
1395 LOG_ERR("%s: unable to read status register", dev->name);
1396 return result;
1397 }
1398
1399 if (ADS114S0X_REGISTER_STATUS_NOT_RDY_GET(status) == 0x01) {
1400 LOG_ERR("%s: ADS114 is not yet ready", dev->name);
1401 return -EBUSY;
1402 }
1403
1404 /*
1405 * Activate internal voltage reference during initialization to
1406 * avoid the necessary setup time for it to settle later on.
1407 */
1408 ADS114S0X_REGISTER_REF_SET_DEFAULTS(reference_control);
1409
1410 result = ads114s0x_write_register(dev, ADS114S0X_REGISTER_REF, reference_control);
1411 if (result != 0) {
1412 LOG_ERR("%s: unable to set default reference control values", dev->name);
1413 return result;
1414 }
1415
1416 /*
1417 * Ensure that the internal voltage reference is active.
1418 */
1419 result = ads114s0x_read_register(dev, ADS114S0X_REGISTER_REF, &reference_control_read);
1420 if (result != 0) {
1421 LOG_ERR("%s: unable to read reference control values", dev->name);
1422 return result;
1423 }
1424
1425 if (reference_control != reference_control_read) {
1426 LOG_ERR("%s: reference control register is incorrect: 0x%02X", dev->name,
1427 reference_control_read);
1428 return -EIO;
1429 }
1430
1431 #ifdef CONFIG_ADC_ADS114S0X_GPIO
1432 data->gpio_enabled = 0x00;
1433 data->gpio_direction = 0x0F;
1434 data->gpio_value = 0x00;
1435
1436 result = ads114s0x_gpio_write_config(dev);
1437
1438 if (result != 0) {
1439 LOG_ERR("%s: unable to configure defaults for GPIOs", dev->name);
1440 return result;
1441 }
1442 #endif
1443
1444 adc_context_unlock_unconditionally(&data->ctx);
1445
1446 return result;
1447 }
1448
1449 static const struct adc_driver_api api = {
1450 .channel_setup = ads114s0x_channel_setup,
1451 .read = ads114s0x_read,
1452 .ref_internal = ADS114S0X_REF_INTERNAL,
1453 #ifdef CONFIG_ADC_ASYNC
1454 .read_async = ads114s0x_adc_read_async,
1455 #endif
1456 };
1457
1458 BUILD_ASSERT(CONFIG_ADC_INIT_PRIORITY > CONFIG_SPI_INIT_PRIORITY,
1459 "CONFIG_ADC_INIT_PRIORITY must be higher than CONFIG_SPI_INIT_PRIORITY");
1460
1461 #define DT_DRV_COMPAT ti_ads114s08
1462
1463 #define ADC_ADS114S0X_INST_DEFINE(n) \
1464 IF_ENABLED( \
1465 CONFIG_ADC_ASYNC, \
1466 (static K_KERNEL_STACK_DEFINE( \
1467 thread_stack_##n, CONFIG_ADC_ADS114S0X_ACQUISITION_THREAD_STACK_SIZE);)) \
1468 static const struct ads114s0x_config config_##n = { \
1469 .bus = SPI_DT_SPEC_INST_GET( \
1470 n, SPI_OP_MODE_MASTER | SPI_MODE_CPHA | SPI_WORD_SET(8), 0), \
1471 IF_ENABLED(CONFIG_ADC_ASYNC, (.stack = thread_stack_##n,)) \
1472 .gpio_reset = GPIO_DT_SPEC_INST_GET_OR(n, reset_gpios, {0}), \
1473 .gpio_data_ready = GPIO_DT_SPEC_INST_GET(n, drdy_gpios), \
1474 .gpio_start_sync = GPIO_DT_SPEC_INST_GET_OR(n, start_sync_gpios, {0}), \
1475 .idac_current = DT_INST_PROP(n, idac_current), \
1476 }; \
1477 static struct ads114s0x_data data_##n; \
1478 DEVICE_DT_INST_DEFINE(n, ads114s0x_init, NULL, &data_##n, &config_##n, POST_KERNEL, \
1479 CONFIG_ADC_INIT_PRIORITY, &api);
1480
1481 DT_INST_FOREACH_STATUS_OKAY(ADC_ADS114S0X_INST_DEFINE);
1482
